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ltc2414/LTC2418 1 241418f applicatio s u features descriptio u typical applicatio u the ltc ? 2414/LTC2418 are 8-/16-channel (4-/8-differ- ential) micropower 24-bit ds analog-to-digital convert- ers. they operate from 2.7v to 5.5v and include an integrated oscillator, 2ppm inl and 0.2ppm rms noise. they use delta-sigma technology and provide single cycle settling time for multiplexed applications. through a single pin, the ltc2414/LTC2418 can be configured for better than 110db differential mode rejection at 50hz or 60hz 2%, or they can be driven by an external oscillator for a user-defined rejection frequency. the internal oscil- lator requires no external frequency setting components. the ltc2414/LTC2418 accept any external differential reference voltage from 0.1v to v cc for flexible ratiometric and remote sensing measurement applications. they can be configured to take 4/8 differential channels or 8/16 single-ended channels. the full-scale bipolar input range is from C 0.5v ref to 0.5v ref . the reference common mode voltage, v refcm , and the input common mode volt- age, v incm , may be independently set within gnd to v cc . the dc common mode input rejection is better than 140db. the ltc2414/LTC2418 communicate through a flexible 4-wire digital interface that is compatible with spi and microwire tm protocols. n direct sensor digitizer n weight scales n direct temperature measurement n gas analyzers n strain gauge transducers n instrumentation n data acquisition n industrial process control , ltc and lt are registered trademarks of linear technology corporation. n 8-/16-channel single-ended or 4-/8-channel differential inputs (ltc2414/LTC2418) n low supply current (200 m a, 4 m a in autosleep) n differential input and differential reference with gnd to v cc common mode range n 2ppm inl, no missing codes n 2.5ppm full-scale error and 0.5ppm offset n 0.2ppm noise n no latency: digital filter settles in a single cycle. each conversion is accurate, even after a new channel is selected n single supply 2.7v to 5.5v operation n internal oscillatorno external components required n 110db min, 50hz/60hz notch filter 8-/16-channel 24-bit no latency ds tm adcs no latency ds is a trademark of linear technology corporation. microwire is a trademark of national semiconductor corporation. total unadjusted error vs input voltage sdi sck sdo cs f o ref + v cc 9 11 2.7v to 5.5v 20 18 17 16 19 1 f com ref gnd 10 thermocouple 12 15 differential 24-bit ? s adc 16-channel mux + 241418 ta01a 4-wire spi interface LTC2418 = 50hz rejection = external oscillator = 60hz rejection v cc ch0 ch1 21 22 ch7 ch8 28 1 ch15 8 input voltage (v) ?.5 ? ? 0 1.0 2.0 tue (ppm of v ref ) 3 2 1 0 ? ? ? ?.5 0.5 0.5 1.5 2414/18 ta01b 2.5 v cc = 5v v ref = 5v v incm = v refcm = 2.5v f o = gnd t a = 85 c t a = 25 c t a = 45 c
ltc2414/LTC2418 2 241418f (notes 1, 2) order part number supply voltage (v cc ) to gnd .......................C 0.3v to 7v analog input voltage to gnd ....... C 0.3v to (v cc + 0.3v) reference input voltage to gnd .. C 0.3v to (v cc + 0.3v) digital input voltage to gnd ........ C 0.3v to (v cc + 0.3v) digital output voltage to gnd ..... C 0.3v to (v cc + 0.3v) t jmax = 125 c, q ja = 110 c/w ltc2414cgn ltc2414ign absolute axi u rati gs w ww u package/order i for atio uu w consult ltc marketing for parts specified with wider operating temperature ranges. operating temperature range ltc2414/LTC2418c ................................ 0 c to 70 c ltc2414/LTC2418i ............................ C 40 c to 85 c storage temperature range ................. C 65 c to 150 c lead temperature (soldering, 10 sec).................. 300 c 1 2 3 4 5 6 7 8 9 10 11 12 13 14 top view gn package 28-lead plastic ssop 28 27 26 25 24 23 22 21 20 19 18 17 16 15 nc nc nc nc nc nc nc nc v cc com ref + ref nc nc ch7 ch6 ch5 ch4 ch3 ch2 ch1 ch0 sdi f o sck sdo cs gnd order part number LTC2418cgn LTC2418ign 1 2 3 4 5 6 7 8 9 10 11 12 13 14 top view gn package 28-lead plastic ssop 28 27 26 25 24 23 22 21 20 19 18 17 16 15 ch8 ch9 ch10 ch11 ch12 ch13 ch14 ch15 v cc com ref + ref nc nc ch7 ch6 ch5 ch4 ch3 ch2 ch1 ch0 sdi f o sck sdo cs gnd t jmax = 125 c, q ja = 110 c/w
ltc2414/LTC2418 3 241418f parameter conditions min typ max units input common mode rejection dc 2.5v ref + v cc , ref C = gnd, l 130 140 db gnd in C = in + 5v (note 5) input common mode rejection 2.5v ref + v cc , ref C = gnd, l 140 db 60hz 2% gnd in C = in + 5v (notes 5, 7) input common mode rejection 2.5v ref + v cc , ref C = gnd, l 140 db 50hz 2% gnd in C = in + 5v (notes 5, 8) input normal mode rejection (notes 5, 7) l 110 140 db 60hz 2% input normal mode rejection (notes 5, 8) l 110 140 db 50hz 2% reference common mode 2.5v ref + v cc , gnd ref C 2.5v, l 130 140 db rejection dc v ref = 2.5v, in C = in + = gnd (note 5) power supply rejection, dc ref + = 2.5v, ref C = gnd, in C = in + = gnd 110 db power supply rejection, 60hz 2% ref + = 2.5v, ref C = gnd, in C = in + = gnd (note 7) 120 db power supply rejection, 50hz 2% ref + = 2.5v, ref C = gnd, in C = in + = gnd (note 8) 120 db the l denotes specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (notes 3, 4) co verter characteristics u parameter conditions min typ max units resolution (no missing codes) 0.1v v ref v cc , C 0.5 ? v ref v in 0.5 ? v ref (note 5) l 24 bits integral nonlinearity 4.5v v cc 5.5v, ref + = 2.5v, ref C = gnd, v incm = 1.25v (note 6) 1 ppm of v ref 5v v cc 5.5v, ref + = 5v, ref C = gnd, v incm = 2.5v (note 6) l 2 14 ppm of v ref ref + = 2.5v, ref C = gnd, v incm = 1.25v (note 6) 5 ppm of v ref offset error 2.5v ref + v cc , ref C = gnd, l 2.5 10 m v gnd in + = in C v cc (note 14) offset error drift 2.5v ref + v cc , ref C = gnd, 20 nv/ c gnd in + = in C v cc positive full-scale error 2.5v ref + v cc , ref C = gnd, l 2.5 12 ppm of v ref in + = 0.75 ? ref + , in C = 0.25 ? ref + positive full-scale error drift 2.5v ref + v cc , ref C = gnd, 0.03 ppm of v ref / c in + = 0.75 ? ref + , in C = 0.25 ? ref + negative full-scale error 2.5v ref + v cc , ref C = gnd, l 2.5 12 ppm of v ref in + = 0.25 ? ref + , in C = 0.75 ? ref + negative full-scale error drift 2.5v ref + v cc , ref C = gnd, 0.03 ppm of v ref / c in + = 0.25 ? ref + , in C = 0.75 ? ref + total unadjusted error 4.5v v cc 5.5v, ref + = 2.5v, ref C = gnd, v incm = 1.25v 3 ppm of v ref 5v v cc 5.5v, ref + = 5v, ref C = gnd, v incm = 2.5v 3 ppm of v ref ref + = 2.5v, ref C = gnd, v incm = 1.25v 6 ppm of v ref output noise 5v v cc 5.5v, ref + = 5v, v ref C = gnd, 1 m v rms gnd in C = in + 5v (note 13) the l denotes specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (notes 3, 4) electrical characteristics
ltc2414/LTC2418 4 241418f symbol parameter conditions min typ max units in + absolute/common mode in + voltage l gnd C 0.3 v cc + 0.3 v in C absolute/common mode in C voltage l gnd C 0.3 v cc + 0.3 v v in input differential voltage range l Cv ref /2 v ref /2 v (in + C in C ) ref + absolute/common mode ref + voltage l 0.1 v cc v ref C absolute/common mode ref C voltage l gnd v cc C 0.1 v v ref reference differential voltage range l 0.1 v cc v (ref + C ref C ) c s (in + )in + sampling capacitance 18 pf c s (in C )in C sampling capacitance 18 pf c s (ref + )ref + sampling capacitance 18 pf c s (ref C )ref C sampling capacitance 18 pf i dc_leak (in + )in + dc leakage current cs = v cc = 5.5v, in + = gnd l C10 1 10 na i dc_leak (in C )in C dc leakage current cs = v cc = 5.5v, in C = 5v l C10 1 10 na i dc_leak (ref + )ref + dc leakage current cs = v cc = 5.5v, ref + = 5v l C10 1 10 na i dc_leak (ref C )ref C dc leakage current cs = v cc = 5.5v, ref C = gnd l C10 1 10 na off channel to in channel isolation dc 140 db (r in = 100 w ) 1hz 140 db f s = 15,3600hz 140 db t open mux break-before-make interval 2.7v v cc 5.5v 70 100 300 ns i s(off) channel off leakage current channel at v cc and gnd l C10 1 10 na the l denotes specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 3) a alog i put a d refere ce u u u u the l denotes specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 3) symbol parameter conditions min typ max units v ih high level input voltage 2.7v v cc 5.5v l 2.5 v cs, f o , sdi 2.7v v cc 3.3v 2.0 v v il low level input voltage 4.5v v cc 5.5v l 0.8 v cs, f o , sdi 2.7v v cc 5.5v 0.6 v v ih high level input voltage 2.7v v cc 5.5v (note 9) l 2.5 v sck 2.7v v cc 3.3v (note 9) 2.0 v v il low level input voltage 4.5v v cc 5.5v (note 9) l 0.8 v sck 2.7v v cc 5.5v (note 9) 0.6 v i in digital input current 0v v in v cc l C10 10 m a cs, f o , sdi i in digital input current 0v v in v cc (note 9) l C10 10 m a sck c in digital input capacitance 10 pf cs, f o , sdi c in digital input capacitance (note 9) 10 pf sck v oh high level output voltage i o = C 800 m a l v cc C 0.5 v sdo digital i puts a d digital outputs u u
ltc2414/LTC2418 5 241418f symbol parameter conditions min typ max units v cc supply voltage l 2.7 5.5 v i cc supply current conversion mode cs = 0v (note 12) l 200 300 m a sleep mode cs = v cc (note 12) l 410 m a sleep mode cs = v cc , 2.7v v cc 3.3v (note 12) 2 m a the l denotes specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 3) power require e ts w u the l denotes specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 3) symbol parameter conditions min typ max units v ol low level output voltage i o = 1.6ma l 0.4 v sdo v oh high level output voltage i o = C 800 m a (note 10) l v cc C 0.5 v sck v ol low level output voltage i o = 1.6ma (note 10) l 0.4 v sck i oz hi-z output leakage l C10 10 m a sdo digital i puts a d digital outputs u u symbol parameter conditions min typ max units f eosc external oscillator frequency range l 2.56 2000 khz t heo external oscillator high period l 0.25 390 m s t leo external oscillator low period l 0.25 390 m s t conv conversion time f o = 0v l 130.86 133.53 136.20 ms f o = v cc l 157.03 160.23 163.44 ms external oscillator (note 11) l 20510/f eosc (in khz) ms f isck internal sck frequency internal oscillator (note 10) 19.2 khz external oscillator (notes 10, 11) f eosc /8 khz d isck internal sck duty cycle (note 10) l 45 55 % f esck external sck frequency range (note 9) l 2000 khz t lesck external sck low period (note 9) l 250 ns t hesck external sck high period (note 9) l 250 ns t dout_isck internal sck 32-bit data output time internal oscillator (notes 10, 12) l 1.64 1.67 1.70 ms external oscillator (notes 10, 11) l 256/f eosc (in khz) ms t dout_esck external sck 32-bit data output time (note 9) l 32/f esck (in khz) ms the l denotes specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 3) ti i g characteristics u w
ltc2414/LTC2418 6 241418f note 1: absolute maximum ratings are those values beyond which the life of the device may be impaired. note 2: all voltage values are with respect to gnd. note 3: v cc = 2.7v to 5.5v unless otherwise specified. v ref = ref + C ref C , v refcm = (ref + + ref C )/2; v in = in + C in C , v incm = (in + + in C )/2, in + and in C are defined as the selected positive and negative input respectively. note 4: f o pin tied to gnd or to v cc or to external conversion clock source with f eosc = 153600hz unless otherwise specified. note 5: guaranteed by design, not subject to test. note 6: integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. the deviation is measured from the center of the quantization band. note 7: f o = 0v (internal oscillator) or f eosc = 153600hz 2% (external oscillator). note 8: f o = v cc (internal oscillator) or f eosc = 128000hz 2% (external oscillator). note 9: the converter is in external sck mode of operation such that the sck pin is used as digital input. the frequency of the clock signal driving sck during the data output is f esck and is expressed in khz. note 10: the converter is in internal sck mode of operation such that the sck pin is used as digital output. in this mode of operation the sck pin has a total equivalent load capacitance c load = 20pf. note 11: the external oscillator is connected to the f o pin. the external oscillator frequency, f eosc , is expressed in khz. note 12: the converter uses the internal oscillator. f o = 0v or f o = v cc . note 13: the output noise includes the contribution of the internal calibration operations. note 14: guaranteed by design and test correlation. symbol parameter conditions min typ max units t 1 cs to sdo low l 0 200 ns t2 cs - to sdo high z l 0 200 ns t3 cs to sck (note 10) l 0 200 ns t4 cs to sck - (note 9) l 50 ns t kqmax sck to sdo valid l 220 ns t kqmin sdo hold after sck (note 5) l 15 ns t 5 sck set-up before cs l 50 ns t 6 sck hold after cs l 50 ns t 7 sdi setup before sck - (note 5) l 100 ns t 8 sdi hold after sck - (note 5) l 100 ns the l denotes specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 3) ti i g characteristics u w
ltc2414/LTC2418 7 241418f typical perfor a ce characteristics uw total unadjusted error (v cc = 5v, v ref = 5v) total unadjusted error (v cc = 5v, v ref = 2.5v) total unadjusted error (v cc = 2.7v, v ref = 2.5v) integral nonlinerity (v cc = 5v, v ref = 5v) integral nonlinerity (v cc = 5v, v ref = 2.5v) integral nonlinerity (v cc = 2.7v, v ref = 2.5v) noise histogram (v cc = 5v, v ref = 5v) noise histogram (v cc = 2.7v, v ref = 2.5v) long term adc readings input voltage (v) ?.5 ?.0 ?.0 0 1.0 2.0 tue (ppm of v ref ) 3 2 1 0 ? ? ? ?.5 0.5 0.5 1.5 241418 g01 2.5 f o = gnd v cc = 5v v ref = 5v v incm = v refcm = 2.5v t a = 25 c t a = 45 c t a = 85 c input voltage (v) ?.25 tue (ppm of v ref ) 3 2 1 0 ? ? ? ?.75 0.25 0.25 0.75 241418 g02 1.25 f o = gnd v cc = 5v v ref = 2.5v v incm = v refcm = 1.25v t a = 25 c t a = 85 c t a = 45 c input voltage (v) ?.25 tue (ppm of v ref ) ?.75 0.25 0.25 0.75 241418 g03 1.25 8 6 4 2 0 ? ? ? ? f o = gnd v cc = 2.7v v ref = 2.5v v incm = v refcm = 1.25v t a = 85 c t a = 45 c t a = 25 c input voltage (v) ?.5 ?.0 ?.0 0 1.0 2.0 inl (ppm of v ref ) 3 2 1 0 ? ? ? ?.5 0.5 0.5 1.5 241418 g04 2.5 f o = gnd v cc = 5v v ref = 5v v incm = v refcm = 2.5v t a = 25 c t a = 45 c t a = 85 c input voltage (v) inl (ppm of v ref ) 3 2 1 0 ? ? ? 241418 g05 f o = gnd v cc = 5v v ref = 2.5v v incm = v refcm = 1.25v t a = 25 c t a = 85 c t a = 45 c ?.25 0.75 0.25 0.25 0.75 1.25 input voltage (v) ?.25 inl (ppm of v ref ) ?.75 0.25 0.25 0.75 241418 g06 1.25 8 6 4 2 0 ? ? ? ? f o = gnd v cc = 2.7v v ref = 2.5v v incm = v refcm = 1.25v t a = 85 c t a = 45 c t a = 25 c output code (ppm of v ref ) ?.2 number of readings (%) 30 25 20 15 10 5 0 ?.6 0 241418 g07 0.6 10,000 consecutive readings f o = gnd t a = 25 c v cc = 5v v ref = 5v v in = 0v v incm = 2.5v gaussian distribution m = 0.24ppm s = 0.183ppm output code (ppm of v ref ) number of readings (%) 14 12 10 8 6 4 2 0 241418 g08 2.4 1.8 1.2 0.6 0 0.6 1.2 10,000 consecutive readings f o = gnd t a = 25 c v cc = 2.7v v ref = 2.5v v in = 0v v incm = 2.5v gaussian distribution m = 0.48ppm s = 0.375ppm time (hours) 0 adc reading (ppm of v ref ) 1.0 0.5 0 0.5 ?.0 ?.5 10 20 30 40 ltxxxx ?tpcxx 50 60 rms noise = 0.19ppm f o = gnd t a = 25 c v cc = 5v v ref = 5v v in = 0v v incm = 2.5v
ltc2414/LTC2418 8 241418f typical perfor a ce characteristics uw rms noise vs input differential voltage rms noise vs v incm rms noise vs temperature (t a ) rms noise vs v cc rms noise vs v ref offset error vs v incm offset error vs temperature offset error vs v cc offset error vs v ref rms noise (ppm of v ref ) 0.5 0.4 0.3 0.2 0.1 0 input differential voltage (v) ?.5 ?.0 ?.0 0 1.0 2.0 ?.5 0.5 0.5 1.5 241418 g10 2.5 f o = gnd t a = 25 c v cc = 5v v ref = 5v v incm = 2.5v v incm (v) ? rms noise ( v) 1.0 0.9 0.8 0.7 0.6 0.5 1 3 4 241418 g11 0 2 5 6 f o = gnd t a = 25 c v cc = 5v ref + = 5v ref = gnd v in = 0v v incm = gnd temperature ( c) rms noise ( m v) 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 241418 g12 ?0 ?5 0 25 50 75 100 f o = gnd v cc = 5v v ref = 5v v in = 0v v incm = gnd v cc (v) 2.7 rms noise ( v) 1.0 0.9 0.8 0.7 0.6 0.5 3.5 4.3 4.7 241418 g13 3.1 3.9 5.1 5.5 f o = gnd t a = 25 c v in = 0v v incm = gnd ref + = 2.5v ref = gnd v ref (v) 0 rms noise ( v) 1.0 0.9 0.8 0.7 0.6 0.5 4 1 2 3 5 241418 g14 f o = gnd t a = 25 c v cc = 5v v in = 0v v incm = gnd ref = gnd v incm (v) ? offset error (ppm of v ref ) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 ?.0 1 3 4 241418 g15 0 2 5 6 f o = gnd t a = 25 c v cc = 5v ref + = 5v ref = gnd v in = 0v temperature ( c) 45 ?0 offset error (ppm of v ref ) 15 30 60 90 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 241418 g16 ?5 0 75 45 f o = gnd v cc = 5v v ref = 5v v in = 0v v incm = gnd v cc (v) 2.7 offset error (ppm of v ref ) 1.0 0.8 0.6 0.4 0.2 0 0.2 0.4 0.6 0.8 ?.0 3.5 4.3 4.7 241418 g17 3.1 3.9 5.1 5.5 f o = gnd t a = 25 c v in = 0v v incm = gnd ref + = 2.5v ref = gnd v ref (v) 0 offset error (ppm of v ref ) 1.0 0.8 0.6 0.4 0.2 0 0.2 0.4 0.6 0.8 ?.0 4 241418 g18 1 2 3 5 f o = gnd t a = 25 c v cc = 5v v in = 0v v incm = gnd ref = gnd
ltc2414/LTC2418 9 241418f typical perfor a ce characteristics uw full-scale error vs temperature full-scale error vs v cc full-scale error vs v ref psrr vs frequency at v cc psrr vs frequency at v cc psrr vs frequency at v cc conversion current vs temperature supply current at elevated output rates (f o over driven) sleep mode current vs temperature temperature ( c) ?0 full-scale error (ppm of v ref ) 5 4 3 2 1 0 ? ? ? ? ? ?0 20 40 241418 g19 ?0 0 60 80 100 +fs error fs error f o = gnd v cc = 5v v ref = 5v v incm = 2.5v v cc (v) 2.7 full-scale error (ppm of v ref ) 5 4 3 2 1 0 ? ? ? ? ? 3.5 3.9 4.3 4.7 5.1 5.5 241418 g20 3.1 +fs error fs error f o = gnd t a = 25 c v ref = 2.5v v incm = 0.5v ref ref = gnd v ref (v) 0 full-scale error (ppm of v ref ) 5 4 3 2 1 0 ? ? ? ? ? 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 241418 g21 0.5 +fs error fs error f o = gnd t a = 25 c v cc = 5v v incm = 0.5v ref ref = gnd frequency at v cc (hz) rejection (db) 0 ?0 ?0 ?0 ?0 ?00 ?20 ?40 241418 g22 1 10 100 1000 10000 100000 1000000 f o = gnd t a = 25 c v cc = 4.1v dc ref + = 2.5v ref = gnd in + = gnd in = gnd sdi = gnd frequency at v cc (hz) 0 rejection (db) 180 241418 g23 60 120 240 0 ?0 ?0 ?0 ?0 ?00 ?20 140 30 90 150 210 f o = gnd t a = 25 c v cc = 4.1v dc 1.4v ref + = 2.5v ref = gnd in + = gnd in = gnd sdi = gnd rejection (db) 241418 g24 0 ?0 ?0 ?0 ?0 ?00 ?20 140 f o = gnd t a = 25 c v cc = 4.1v dc 0.7v p-p ref + = 2.5v ref = gnd in + = gnd in = gnd sdi = gnd frequency at v cc (hz) 15250 15300 15350 15400 15450 temperature ( c) 45 ?0 ?5 conversion current ( a) 90 241418 g25 0 15 30 75 60 45 240 230 220 210 200 190 180 170 160 cs = gnd f o = gnd sck = nc sdo = nc sdi = gnd v cc = 5.5v v cc = 5v v cc = 3v v cc = 2.7v supply current ( a) 1000 900 800 700 600 500 400 300 200 100 output data rate (readings/sec) 241418 g26 0 102030 40 50 60 70 80 90 100 cs = gnd f o = ext osc in + = gnd in = gnd sck = nc sdo = nc sdi = gnd t a = 25 c v ref = v cc v cc = 5v v cc = 3v temperature ( c) 45 ?0 ?5 sleep-mode current ( a) 90 241418 g27 0 15 30 75 60 45 6 5 4 3 2 1 0 cs = v cc f o = gnd sck = nc sdo = nc sdi = gnd v cc = 5.5v v cc = 5v v cc = 3v v cc = 2.7v
ltc2414/LTC2418 10 241418f ch0 to ch15 (pin 21 to pin 28 and pin 1 to pin 8): analog inputs. may be programmed for single-ended or differen- tial mode. ch8 to ch15 (pin 1 to pin 8) not connected on the ltc2414. v cc (pin 9): positive supply voltage. bypass to gnd (pin 15) with a 10 m f tantalum capacitor in parallel with 0.1 m f ceramic capacitor as close to the part as possible. com (pin 10): the common negative input (in C ) for all single-ended multiplexer configurations. the voltage on channel 0 to 15 and com input pins can have any value between gnd C 0.3v and v cc + 0.3v. within these limits, the two selected inputs (in + and in C ) provide a bipolar input range (v in = in + C in C ) from C 0.5 ? v ref to 0.5 ? v ref . outside this input range, the converter produces unique overrange and underrange output codes. ref + (pin 11), ref C (pin 12): differential reference input. the voltage on these pins can have any value between gnd and v cc as long as the positive reference input, ref + , is maintained more positive than the negative reference input, ref C , by at least 0.1v. gnd (pin 15): ground. connect this pin to a ground plane through a low impedance connection. cs (pin 16): active low digital input. a low on this pin enables the sdo digital output and wakes up the adc. following each conversion the adc automatically enters the sleep mode and remains in this low power state as long as cs is high. a low-to-high transition on cs during the data output transfer aborts the data transfer and starts a new conversion. sdo (pin 17): three-state digital output. during the data output period, this pin is used as the serial data output. when the chip select cs is high (cs = v cc ), the sdo pin is in a high impedance state. during the conversion and sleep periods, this pin is used as the conversion status output. the conversion status can be observed by pulling cs low. sck (pin 18): bidirectional digital clock pin. in internal serial clock operation mode, sck is used as the digital output for the internal serial interface clock during the data output period. in external serial clock operation mode, sck is used as the digital input for the external serial interface clock during the data output period. a weak internal pull-up is automatically activated in internal serial clock operation mode. the serial clock operation mode is determined by the logic level applied to the sck pin at power up or during the most recent falling edge of cs. f o (pin 19): frequency control pin. digital input that controls the adcs notch frequencies and conversion time. when the f o pin is connected to v cc (f o = v cc ), the converter uses its internal oscillator and the digital filter first null is located at 50hz. when the f o pin is connected to gnd (f o = 0v), the converter uses its internal oscillator and the digital filter first null is located at 60hz. when f o is driven by an external clock signal with a frequency f eosc , the converters use this signal as their system clock and the digital filter first null is located at a frequency f eosc /2560. sdi (pin 20): serial digital data input. during the data output period, this pin is used to shift in the multiplexer address started from the first rising sck edge. during the conversion and sleep periods, this pin is in the dont care state. however, a high or low logic level should be maintained on sdi in the dont care mode to avoid an excessive current in the sdi input buffers. nc pins: do not connect. uu u pi fu ctio s
ltc2414/LTC2418 11 241418f cs is high. while in the sleep state, power consumption is reduced by nearly two orders of magnitude. the conver- sion result is held indefinitely in a static shift register while the converter is in the sleep state. once cs is pulled low, the device exits the low power mode and enters the data output state. if cs is pulled high before the first rising edge of sck, the device returns to the low power sleep mode and the conversion result is still held in the internal static shift register. if cs remains low after the first rising edge of sck, the device begins output- ting the conversion result and inputting channel selection bits. taking cs high at this point will terminate the data output state and start a new conversion. the channel selection control bits are shifted in through sdi from the figure 1 uu w fu ctio al block diagra test circuits autocalibration and control differential 3rd order ? s modulator decimating fir address internal oscillator serial interface gnd v cc ch0 ch1 ch15 com in + in mux sdo sck ref + ref cs sdi f o (int/ext) 241418 f01 + 1.69k sdo 241418 ta02 hi-z to v oh v ol to v oh v oh to hi-z c load = 20pf 1.69k sdo 241418 ta03 hi-z to v ol v oh to v ol v ol to hi-z c load = 20pf v cc converter operation converter operation cycle the ltc2414/LTC2418 are multichannel, low power, delta- sigma analog-to-digital converters with an easy-to-use 4-wire serial interface (see figure 1). their operation is made up of three states. the converter operating cycle begins with the conversion, followed by the low power sleep state and ends with the data input/output (see figure 2). the 4-wire interface consists of serial data input (sdi), serial data out- put (sdo), serial clock (sck) and chip select (cs). initially, the ltc2414 or LTC2418 performs a conversion. once the conversion is complete, the device enters the sleep state. the part remains in the sleep state as long as applicatio s i for atio wu uu
ltc2414/LTC2418 12 241418f first rising edge of sck and depending on the control bits, the converter updates its channel selection immediately and is valid for the next conversion. the details of channel selection control bits are described in the input data mode section. the output data is shifted out the sdo pin under the control of the serial clock (sck). the output data is updated on the falling edge of sck allowing the user to reliably latch data on the rising edge of sck (see figure 3). the data output state is concluded once 32 bits are read out of the adc or when cs is brought high. the device automatically initiates a new conversion and the cycle repeats. through timing control of the cs and sck pins, the ltc2414/LTC2418 offer several flexible modes of opera- tion (internal or external sck and free-running conversion modes). these various modes do not require program- ming configuration registers; moreover, they do not dis- turb the cyclic operation described above. these modes of operation are described in detail in the serial interface timing modes section. conversion clock a major advantage the delta-sigma converter offers over conventional type converters is an on-chip digital filter (commonly implemented as a sinc or comb filter). for high resolution, low frequency applications, this filter is typically designed to reject line frequencies of 50hz or applicatio s i for atio wu uu figure 2. ltc2414/LTC2418 state transition diagram convert power up in + = ch0, in = ch1 sleep data output address input 241418 f02 true false cs = low and sck 60hz plus their harmonics. the filter rejection perfor- mance is directly related to the accuracy of the converter system clock. the ltc2414/LTC2418 incorporate a highly accurate on-chip oscillator. this eliminates the need for external frequency setting components such as crystals or oscillators. clocked by the on-chip oscillator, the ltc2414/ LTC2418 achieve a minimum of 110db rejection at the line frequency (50hz or 60hz 2%). ease of use the ltc2414/LTC2418 data output has no latency, filter settling delay or redundant data associated with the conversion cycle. there is a one-to-one correspondence between the conversion and the output data. therefore, multiplexing multiple analog voltages is easy. the ltc2414/LTC2418 perform offset and full-scale cali- brations in every conversion cycle. this calibration is trans- parent to the user and has no effect on the cyclic operation described above. the advantage of continuous calibration is extreme stability of offset and full-scale readings with re- spect to time, supply voltage change and temperature drift. power-up sequence the ltc2414/LTC2418 automatically enter an internal reset state when the power supply voltage v cc drops below approximately 2v. this feature guarantees the integrity of the conversion result and of the serial interface mode selection. (see the 3-wire i/o sections in the serial interface timing modes section.) when the v cc voltage rises above this critical threshold, the converter creates an internal power-on-reset (por) signal with a typical duration of 1ms. the por signal clears all internal registers. following the por signal, the ltc2414/LTC2418 start a normal conversion cycle and follow the succession of states described above. the first conversion result following por is accurate within the specifications of the device if the power supply voltage is restored within the operating range (2.7v to 5.5v) before the end of the por time interval. reference voltage range the ltc2414/LTC2418 accept a truly differential external reference voltage. the absolute/common mode voltage
ltc2414/LTC2418 13 241418f specification for the ref + and ref C pins covers the entire range from gnd to v cc . for correct converter operation, the ref + pin must always be more positive than the ref C pin. the ltc2414/LTC2418 can accept a differential reference voltage from 0.1v to v cc . the converter output noise is determined by the thermal noise of the front-end circuits, and, as such, its value in nanovolts is nearly constant with reference voltage. a decrease in reference voltage will not significantly improve the converters effective resolution. on the other hand, a reduced reference voltage will im- prove the converters overall inl performance. a reduced reference voltage will also improve the converter perfor- mance when operated with an external conversion clock (external f o signal) at substantially higher output data rates. input voltage range the two selected pins are labeled in + and in C (see tables 1 and 2). once selected (either differential or single-ended multiplexing mode), the analog input is differential with a common mode range for the in + and in C input pins ex- tending from gnd C 0.3v to v cc + 0.3v. outside these limits, the esd protection devices begin to turn on and the errors due to input leakage current increase rap- idly. within these limits, the ltc2414/LTC2418 convert the bipolar differential input signal, v in = in + C in C , from C fs = C 0.5 ? v ref to +fs = 0.5 ? v ref where v ref = ref + C ref C . outside this range the converters indicate the overrange or the underrange condition using distinct output codes. input signals applied to in + and in C pins may extend 300mv below ground or above v cc . in order to limit any fault current, resistors of up to 5k may be added in series with the in + or in C pins without affecting the performance of the device. in the physical layout, it is important to maintain the parasitic capacitance of the connection be- tween these series resistors and the corresponding pins as low as possible; therefore, the resistors should be located as close as practical to the pins. in addition, series resistors will introduce a temperature dependent offset error due to the input leakage current. a 1na input leakage current will develop a 1ppm offset error on a 5k resistor if v ref = 5v. this error has a very strong temperature dependency. input data format when the ltc2414/LTC2418 are powered up, the default selection used for the first conversion is in + = ch0 and in C = ch1 (address = 00000). in the data input/output mode following the first conversion, a channel selection can be updated using an 8-bit word. the ltc2414/LTC2418 serial input data is clocked into the sdi pin on the rising edge of sck (see figure 3). the input is composed of an 8-bit word with the first 3 bits acting as control bits and the remaining 5 bits as the channel address bits. the first 2 bits are always 10 for proper updating opera- tion. the third bit is en. for en = 1, the following 5 bits are used to update the input channel selection. for en = 0, previous channel selection is kept and the following bits are ignored. therefore, the address is updated when the 3 control bits are 101 and kept for 100. alternatively, the 3 control bits can be all zero to keep the previous address. this alternation is intended to simplify the sdi interface allowing the user to simply connect sdi to ground if no update is needed. combinations other than 101, 100 and 000 of the 3 control bits should be avoided. when update operation is set (101), the following 5 bits are the channel address. the first bit, sgl, decides if the differential selection mode (sgl = 0) or the single-ended selection mode is used (sgl = 1). for sgl = 0, two adjacent channels can be selected to form a differential input; for sgl = 1, one of the 8 channels (ch0-ch7) for the ltc2414 or one of the 16 channels (ch0-ch15) for the LTC2418 is selected as the positive input and the com pin is used as the negative input. for the ltc2414, the lower half channels (ch0-ch7) are used and the channel ad- dress bit a2 should be always 0, see table 1. while for the LTC2418, all the 16 channels are used and the size of the corresponding selection table (table 2) is doubled from that of the ltc2414 (table 1). for a given channel selec- tion, the converter will measure the voltage between the two channels indicated by in + and in C in the selected row of tables 1 or 2. applicatio s i for atio wu uu
ltc2414/LTC2418 14 241418f applicatio s i for atio wu uu figure 3a. input/output data timing cs sdo hi-z sig dmy bit29 msb b22 converson result bit28 bit27 bit26 bit25 bit24 lsb bit6 sgl bit5 a2 bit3 a1 bit2 a0 bit1 parity bit0 odd/ sign bit4 bit30 sck sdi sleep data input/output bit31 eoc 1 0 en sgl a2 a1 a0 don? care conversion 241418 f03a odd/ sign address corresponding to result address n ?1 conversion result n ?1 address n address n + 1 address n + 2 output n ?1 output n output n + 1 sdo sck sdi operation hi-z don? care conversion n 241418 f03b conversion n + 1 don? care hi-z hi-z conversion result n conversion result n + 1 address n address n + 1 figure 3b. typical operation sequence table 1. channel selection for the ltc2414 (bit a2 should always be 0) mux address channel selection odd/ sgl sign a2 a1 a0 01234567com *0 0 000 in + in C 0 0 001 in + in C 0 0 010 in + in C 0 0 011 in + in C 0 1 000 in C in + 0 1 001 in C in + 0 1 010 in C in + 0 1 011 in C in + 1 0 000 in + in C 1 0 001 in + in C 1 0 010 in + in C 1 0 011 in + in C 1 1 000 in + in C 1 1 001 in + in C 1 1 010 in + in C 1 1 011 in + in C *default at power up
ltc2414/LTC2418 15 241418f table 2. channel selection for the LTC2418 mux address channel selection odd/ sgl sign a2 a1 a0 0 123456789101112131415com *00000in + in C 00001 in + in C 00010 in + in C 00011 in + in C 00100 in + in C 00101 in + in C 00110 in + in C 00111 in + in C 01000in C in + 01001 in C in + 01010 in C in + 01011 in C in + 01100 in C in + 01101 in C in + 01110 in C in + 01111 in C in + 10000in + in C 10001 in + in C 10010 in + in C 10011 in + in C 10100 in + in C 10101 in + in C 10110 in + in C 10111 in + in C 11000 in + in C 11001 in + in C 11010 in + in C 11011 in + in C 11100 in + in C 11101 in + in C 11110 in + in C 11111 in + in C *default at power up applicatio s i for atio wu uu output data format the ltc2414/LTC2418 serial output data stream is 32 bits long. the first 3 bits represent status information indicat- ing the sign and conversion state. the next 23 bits are the conversion result, msb first. the next 5 bits (bit 5 to bit 1) indicate which channel the conversion just performed was selected. the address bits programmed during this data output phase select the input channel for the next conver- sion cycle. these address bits are output during the sub- sequent data read, as shown in figure 3b. the last bit is a
ltc2414/LTC2418 16 241418f parity bit representing the parity of the previous 31 bits. the parity bit is useful to check the output data integrity espe- cially when the output data is transmitted over a distance. the third and fourth bits together are also used to indicate an underrange condition (the differential input voltage is be- low C fs) or an overrange condition (the differential input voltage is above + fs). bit 31 (first output bit) is the end of conversion (eoc) indicator. this bit is available at the sdo pin during the conversion and sleep states whenever the cs pin is low. this bit is high during the conversion and goes low when the conversion is complete. bit 30 (second output bit) is a dummy bit (dmy) and is always low. bit 29 (third output bit) is the conversion result sign indi- cator (sig). if v in is >0, this bit is high. if v in is <0, this bit is low. bit 28 (fourth output bit) is the most significant bit (msb) of the result. this bit in conjunction with bit 29 also provides the underrange or overrange indication. if both bit 29 and bit 28 are high, the differential input voltage is above +fs. if both bit 29 and bit 28 are low, the differential input voltage is below Cfs. the function of these bits is summarized in table 3. table 3. ltc2414/LTC2418 status bits bit 31 bit 30 bit 29 bit 28 input range eoc dmy sig msb v in 3 0.5 ? v ref 0011 0v v in < 0.5 ? v ref 0010 C0.5 ? v ref v in < 0v 0 0 0 1 v in < C 0.5 ? v ref 0000 bits 28-6 are the 23-bit conversion result msb first. bit 6 is the least significant bit (lsb). bits 5-1 are the corresponding channel selection bits for the present conversion result with bit sgl output first as shown in figure 3. bit 0 is the parity bit representing the parity of the previous 31 bits. including the parity bit, the total numbers of 1s and 0s in the output data are always even. data is shifted out of the sdo pin under control of the serial clock (sck), see figure 3. whenever cs is high, sdo remains high impedance and any externally generated sck clock pulses are ignored by the internal data out shift register. in order to shift the conversion result out of the device, cs must first be driven low. eoc is seen at the sdo pin of the device once cs is pulled low. eoc changes real time from high to low at the completion of a conversion. this signal may be used as an interrupt for an external micro- controller. bit 31 (eoc) can be captured on the first rising edge of sck. bit 30 is shifted out of the device on the first falling edge of sck. the final data bit (bit 0) is shifted out on the falling edge of the 31st sck and may be latched on the rising edge of the 32nd sck pulse. on the falling edge of the 32nd sck pulse, sdo goes high indicating the initiation of a new conversion cycle. this bit serves as eoc (bit 31) for the next conversion cycle. table 4 summarizes the output data format. as long as the voltage applied to any channel (ch0-ch15, com) is maintained within the C 0.3v to (v cc + 0.3v) absolute maximum operating range, a conversion result is generated for any differential input voltage v in from Cfs = C 0.5 ? v ref to +fs = 0.5 ? v ref . for differential input voltages greater than +fs, the conversion result is clamped to the value corresponding to the +fs + 1lsb. for differ- ential input voltages below Cfs, the conversion result is clamped to the value corresponding to Cfs C 1lsb. frequency rejection selection (f o ) the ltc2414/LTC2418 internal oscillator provides better than 110db normal mode rejection at the line frequency and all its harmonics for 50hz 2% or 60hz 2%. for 60hz rejection, f o should be connected to gnd while for 50hz rejection the f o pin should be connected to v cc . the selection of 50hz or 60hz rejection can also be made by driving f o to an appropriate logic level. a selection change during the sleep or data output states will not disturb the converter operation. if the selection is made during the conversion state, the result of the conversion in progress may be outside specifications but the following conversions will not be affected. applicatio s i for atio wu uu
ltc2414/LTC2418 17 241418f when a fundamental rejection frequency different from 50hz or 60hz is required or when the converter must be synchronized with an outside source, the ltc2414/ LTC2418 can operate with an external conversion clock. the converter automatically detects the presence of an external clock signal at the f o pin and turns off the internal oscillator. the frequency f eosc of the external signal must be at least 2560hz (1hz notch frequency) to be detected. the external clock signal duty cycle is not significant as long as the minimum and maximum specifications for the high and low periods t heo and t leo are observed. while operating with an external conversion clock of a frequency f eosc , the converter provides better than 110db normal mode rejection in a frequency range f eosc /2560 4% and its harmonics. the normal mode rejection as a function of the input frequency deviation from f eosc /2560 is shown in figure 4. whenever an external clock is not present at the f o pin, the converter automatically activates its internal oscillator and enters the internal conversion clock mode. the converter operation will not be disturbed if the change of conversion clock source occurs during the sleep state or during the data output state while the converter uses an external serial clock. if the change occurs during the conversion state, the result of the conversion in progress may be outside specifications but the following conversions will not be affected. if the change occurs during the data output state and the converter is in the internal sck mode, the serial clock duty cycle may be affected but the serial data stream will remain valid. table 5 summarizes the duration of each state and the achievable output data rate as a function of f o . serial interface pins the ltc2414/LTC2418 transmit the conversion results and receive the start of conversion command through a synchronous 4-wire interface. during the conversion and sleep states, this interface can be used to assess the con- verter status and during the data i/o state it is used to read the conversion result and write in channel selection bits. figure 4. ltc2414/LTC2418 normal mode rejection when using an external oscillator of frequency f eosc differential input signal frequency deviation from notch frequency f eosc /2560(%) 128404812 normal mode rejection (db) 241418 f04 ?0 ?5 ?0 ?5 100 105 110 115 120 125 130 135 140 applicatio s i for atio wu uu table 4. ltc2414/LTC2418 output data format differential input voltage bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 6 v in * eoc dmy sig msb lsb v in * 3 0.5 ? v ref ** 0 0110 0 00 0.5 ? v ref ** C 1lsb 0 0101 1 11 0.25 ? v ref ** 0 0101 0 00 0.25 ? v ref ** C 1lsb 0 0100 1 11 0 0 0100 0 00 C1lsb 0 0011 1 11 C 0.25 ? v ref ** 0 0011 0 00 C 0.25 ? v ref ** C 1lsb 0 0010 1 11 C 0.5 ? v ref ** 0 0010 0 00 v in * < C0.5 ? v ref ** 0 0001 1 11 *the differential input voltage v in = in + C in C . **the differential reference voltage v ref = ref + C ref C .
ltc2414/LTC2418 18 241418f table 5. ltc2414/LTC2418 state duration state operating mode duration convert internal oscillator f o = low 133ms, output data rate 7.5 readings/s (60hz rejection) f o = high 160ms, output data rate 6.2 readings/s (50hz rejection) external oscillator f o = external oscillator 20510/f eosc s, output data rate f eosc /20510 readings/s with frequency f eosc khz (f eosc /2560 rejection) sleep as long as cs = high until cs = low and sck data output internal serial clock f o = low/high as long as cs = low but not longer than 1.67ms (internal oscillator) (32 sck cycles) f o = external oscillator with as long as cs = low but not longer than 256/f eosc ms frequency f eosc khz (32 sck cycles) external serial clock with as long as cs = low but not longer than 32/f sck ms frequency f sck khz (32 sck cycles) serial clock input/output (sck) the serial clock signal present on sck (pin 18) is used to synchronize the data transfer. each bit of data is shifted out the sdo pin on the falling edge of the serial clock and each input bit is shifted in the sdi pin on the rising edge of the serial clock. in the internal sck mode of operation, the sck pin is an output and the ltc2414/LTC2418 create their own serial clock by dividing the internal conversion clock by 8. in the external sck mode of operation, the sck pin is used as input. the internal or external sck mode is selected on power-up and then reselected every time a high-to-low transition is detected at the cs pin. if sck is high or float- ing at power-up or during this transition, the converter enters the internal sck mode. if sck is low at power-up or during this transition, the converter enters the external sck mode. serial data input (sdi) the serial data input pin, sdi (pin 20), is used to shift in the channel control bits during the data output state to prepare the channel selection for the following conversion. when cs (pin 16) is high or the converter is in the con- version state, the sdi input is ignored and may be driven high or low. when cs goes low and the conversion is complete, sdo goes low and then sdi starts to shift in bits on the rising edge of sck. serial data output (sdo) the serial data output pin, sdo (pin 17), provides the result of the last conversion as a serial bit stream (msb first) during the data output state. in addition, the sdo pin is used as an end of conversion indicator during the conversion and sleep states. when cs (pin 16) is high, the sdo driver is switched to a high impedance state. this allows sharing the serial interface with other devices. if cs is low during the convert or sleep state, sdo will output eoc. if cs is low during the conversion phase, the eoc bit appears high on the sdo pin. once the conversion is complete, eoc goes low. the device remains in the sleep state until the first rising edge of sck occurs while cs = low. chip select input (cs) the active low chip select, cs (pin 16), is used to test the conversion status and to enable the data input/output transfer as described in the previous sections. in addition, the cs signal can be used to trigger a new conversion cycle before the entire serial data transfer has been completed. the ltc2414/LTC2418 will abort any serial data transfer in progress and start a new conversion cycle anytime a low-to-high transition is detected at the cs pin after the converter has entered the data input/ output state (i.e., after the first rising edge of sck occurs with cs = low). if the device has not finished loading the applicatio s i for atio wu uu
ltc2414/LTC2418 19 241418f table 6. ltc2414/LTC2418 interface timing modes conversion data connection sck cycle output and configuration source control control waveforms external sck, single cycle conversion external cs and sck cs and sck figures 5, 6 external sck, 3-wire i/o external sck sck figure 7 internal sck, single cycle conversion internal cs cs figures 8, 9 internal sck, 3-wire i/o, continuous conversion internal continuous internal figure 10 last input bit a0 of sdi by the time cs pulled high, the address information is discarded and the previous address is kept. finally, cs can be used to control the free-running modes of operation, see serial interface timing modes section. grounding cs will force the adc to continuously convert at the maximum output rate selected by f o . serial interface timing modes the ltc2414/LTC2418s 4-wire interface is spi and microwire compatible. this interface offers several flexible modes of operation. these include internal/exter- nal serial clock, 3- or 4-wire i/o, single cycle conversion. the following sections describe each of these serial inter- face timing modes in detail. in all these cases, the con- verter can use the internal oscillator (f o = low or f o = high) or an external oscillator connected to the f o pin. refer to table 6 for a summary. external serial clock, single cycle operation (spi/microwire compatible) this timing mode uses an external serial clock to shift out the conversion result and a cs signal to monitor and control the state of the conversion cycle, see figure 5. applicatio s i for atio wu uu figure 5. external serial clock, single cycle operation eoc bit 31 sdo sck (external) cs (1) (0) en sgl a2 a1 a0 odd/ sign sdi don? care test eoc parity msb sig bit 0 lsb bit 6 bit 27 bit 26 bit 25 bit 24 bit 28 bit 29 bit 30 sleep sleep data output conversion 241418 f05 conversion hi-z hi-z hi-z test eoc v cc f o ref + ref ch0 ch7 ch8 ch15 com sck sdi sdo cs gnd 920 11 12 21 28 1 8 10 18 17 15 16 19 reference voltage 0.1v to v cc analog inputs = 50hz rejection = external oscillator = 60hz rejection v cc 1 f 2.7v to 5.5v ltc2414/ LTC2418 4-wire spi interface don? care test eoc (optional)
ltc2414/LTC2418 20 241418f the serial clock mode is selected on the falling edge of cs. to select the external serial clock mode, the serial clock pin (sck) must be low during each cs falling edge. the serial data output pin (sdo) is hi-z as long as cs is high. at any time during the conversion cycle, cs may be pulled low in order to monitor the state of the converter. while cs is pulled low, eoc is output to the sdo pin. eoc = 1 while a conversion is in progress and eoc = 0 if the device is in the sleep state. independent of cs, the device automatically enters the low power sleep state once the conversion is complete. when the device is in the sleep state, its conversion result is held in an internal static shift register. the device remains in the sleep state until the first rising edge of sck is seen while cs is low. the input data is then shifted in via the sdi pin on the rising edge of sck (including the first rising edge) and the output data is shifted out of the sdo pin on each falling edge of sck . this enables external circuitry to latch the output on the rising edge of sck. eoc can be latched on the first rising edge of sck and the last bit of the conversion result can be latched on the 32nd rising edge of sck. on the 32nd falling edge of sck, the device begins a new conversion. sdo goes high (eoc = 1) indicating a conversion is in progress. at the conclusion of the data cycle, cs may remain low and eoc monitored as an end-of-conversion interrupt. alternatively, cs may be driven high setting sdo to hi-z. as described above, cs may be pulled low at any time in order to monitor the conversion status. typically, cs remains low during the data output state. however, the data output state may be aborted by pulling cs high anytime between the first rising edge and the 32nd falling edge of sck, see figure 6. on the rising edge of cs, the device aborts the data output state and immediately initiates a new conversion. if the device has not finished loading the last input bit a0 of sdi by the time cs is pulled high, the address information is discarded and the previ- ous address is kept. this is useful for systems not requir- ing all 32 bits of output data, aborting an invalid conversion cycle or synchronizing the start of a conversion. figure 6. external serial clock, reduced data output length applicatio s i for atio wu uu (1) (0) en sgl a2 a1 a0 odd/ sign sdi don? care don? care sdo sck (external) cs data output conversion sleep sleep sleep test eoc data output hi-z hi-z hi-z conversion 241418 f06 msb sig bit 8 bit 27 bit 26 bit 25 bit 24 bit 9 bit 28 bit 29 bit 30 eoc bit 31 bit 0 eoc hi-z test eoc v cc f o ref + ref ch0 ch7 ch8 ch15 com sck sdi sdo cs gnd 920 11 12 21 28 1 8 10 18 17 15 16 19 reference voltage 0.1v to v cc analog inputs = 50hz rejection = external oscillator = 60hz rejection v cc 1 f 2.7v to 5.5v ltc2414/ LTC2418 4-wire spi interface test eoc (optional)
ltc2414/LTC2418 21 241418f figure 7. external serial clock, cs = 0 operation external serial clock, 3-wire i/o this timing mode utilizes a 3-wire serial i/o interface. the conversion result is shifted out of the device by an exter- nally generated serial clock (sck) signal, see figure 7. cs may be permanently tied to ground, simplifying the user interface or isolation barrier. the external serial clock mode is selected at the end of the power-on reset (por) cycle. the por cycle is concluded typically 1ms after v cc exceeds approximately 2v. the level applied to sck at this time determines if sck is internal or external. sck must be driven low prior to the end of por in order to enter the external serial clock timing mode. since cs is tied low, the end-of-conversion (eoc) can be continuously monitored at the sdo pin during the convert and sleep states. eoc may be used as an interrupt to an external controller indicating the conversion result is ready. eoc = 1 while the conversion is in progress and eoc = 0 once the conversion ends. on the falling edge of eoc, the conversion result is loaded into an internal static shift register. the input data is then shifted in via the sdi pin on the rising edge of sck (including the first rising edge) and the output data is shifted out of the sdo pin on each falling edge of sck. eoc can be latched on the first rising edge of sck. on the 32nd falling edge of sck, sdo goes high (eoc = 1) indicating a new conversion has begun. internal serial clock, single cycle operation this timing mode uses an internal serial clock to shift out the conversion result and a cs signal to monitor and control the state of the conversion cycle, see figure 8. in order to select the internal serial clock timing mode, the serial clock pin (sck) must be floating (hi-z) or pulled high prior to the falling edge of cs. the device will not enter the internal serial clock mode if sck is driven low on the falling edge of cs. an internal weak pull-up resistor is active on the sck pin during the falling edge of cs; therefore, the internal serial clock timing mode is auto- matically selected if sck is not externally driven. the serial data output pin (sdo) is hi-z as long as cs is high. at any time during the conversion cycle, cs may be pulled low in order to monitor the state of the converter. once cs is pulled low, sck goes low and eoc is output to the sdo pin. eoc = 1 while a conversion is in progress and eoc = 0 if the device is in the sleep state. applicatio s i for atio wu uu (1) (0) en sgl a2 a1 a0 odd/ sign sdi don? care don? care eoc bit 31 sdo sck (external) cs msb sig bit 0 parity lsb bit 6 bit 27 bit 26 bit 25 bit 24 bit 28 bit 29 bit 30 data output conversion 241418 f07 conversion v cc f o ref + ref ch0 ch7 ch8 ch15 com sck sdi sdo cs gnd 920 11 12 21 28 1 8 10 18 17 15 16 19 reference voltage 0.1v to v cc analog inputs = 50hz rejection = external oscillator = 60hz rejection v cc 1 f 2.7v to 5.5v ltc2414/ LTC2418 3-wire spi interface
ltc2414/LTC2418 22 241418f when testing eoc, if the conversion is complete (eoc = 0), the device will exit the low power mode during the eoc test. in order to allow the device to return to the low power sleep state, cs must be pulled high before the first rising edge of sck. in the internal sck timing mode, sck goes high and the device begins outputting data at time t eoctest after the falling edge of cs (if eoc = 0) or t eoctest after eoc goes low (if cs is low during the falling edge of eoc). the value of t eoctest is 23 m s if the device is using its internal oscillator (f o = logic low or high). if f o is driven by an external oscillator of frequency f eosc , then t eoctest is 3.6/f eosc . if cs is pulled high before time t eoctest , the device returns to the sleep state and the conversion result is held in the internal static shift register. if cs remains low longer than t eoctest , the first rising edge of sck will occur and the conversion result is serially shifted out of the sdo pin. the data i/o cycle concludes after the 32nd rising edge. the input data is then shifted in via the sdi pin on the rising edge of sck (including the first rising edge) and the output data is shifted out of the sdo pin on each falling edge of sck. the internally generated serial clock is output to the sck pin. this signal may be used to shift the conversion result into external circuitry. eoc can be latched on the first rising edge of sck and the last bit of the conversion result on the 32nd rising edge of sck. after the 32nd rising edge, sdo goes high (eoc = 1), sck stays high and a new conversion starts. typically, cs remains low during the data output state. however, the data output state may be aborted by pulling cs high anytime between the first and 32nd rising edge of sck, see figure 9. on the rising edge of cs, the device aborts the data output state and immediately initiates a new conversion. if the device has not finished loading the last input bit a0 of sdi by the time cs is pulled high, the address information is discarded and the previous ad- dress is still kept. this is useful for systems not requiring all 32 bits of output data, aborting an invalid conversion cycle, or synchronizing the start of a conversion. if cs is pulled high while the converter is driving sck low, the internal pull-up is not available to restore sck to a logic high state. this will cause the device to exit the internal serial clock mode on the next falling edge of cs. this can be avoided by adding an external 10k pull-up resistor to the sck pin or by never pulling cs high when sck is low. applicatio s i for atio wu uu figure 8. internal serial clock, single cycle operation (1) (0) en sgl a2 a1 a0 odd/ sign sdi don? care don? care sdo sck (internal) cs msb sig bit 0 lsb parity bit 6 test eoc bit 27 bit 26 bit 25 bit 24 bit 28 bit 29 bit 30 eoc bit 31 sleep sleep data output conversion conversion 241418 f08 LTC2418 4-wire spi interface v cc 10k
ltc2414/LTC2418 23 241418f whenever sck is low, the ltc2414/LTC2418s internal pull-up at pin sck is disabled. normally, sck is not exter- nally driven if the device is in the internal sck timing mode. however, certain applications may require an external driver on sck. if this driver goes hi-z after outputting a low signal, the ltc2414/LTC2418s internal pull-up remains disabled. hence, sck remains low. on the next falling edge of cs, the device is switched to the external sck timing mode. by adding an external 10k pull-up resistor to sck, this pin goes high once the external driver goes hi-z. on the next cs falling edge, the device will remain in the in- ternal sck timing mode. a similar situation may occur during the sleep state when cs is pulsed high-low-high in order to test the conver- sion status. if the device is in the sleep state (eoc = 0), sck will go low. once cs goes high (within the time period defined above as t eoctest ), the internal pull-up is activated. for a heavy capacitive load on the sck pin, the internal pull-up may not be adequate to return sck to a high level before cs goes low again. this is not a concern under normal conditions where cs remains low after detecting eoc = 0. this situation is easily overcome by adding an external 10k pull-up resistor to the sck pin. internal serial clock, 3-wire i/o, continuous conversion this timing mode uses a 3-wire interface. the conversion result is shifted out of the device by an internally generated serial clock (sck) signal, see figure 10. cs may be perma- nently tied to ground, simplifying the user interface or isolation barrier. the internal serial clock mode is selected at the end of the power-on reset (por) cycle. the por cycle is concluded approximately 1ms after v cc exceeds 2v. an internal weak pull-up is active during the por cycle; therefore, the internal serial clock timing mode is automatically selected if sck is not externally driven low (if sck is loaded such that the internal pull-up cannot pull the pin high, the external sck mode will be selected). during the conversion, the sck and the serial data output pin (sdo) are high (eoc = 1). once the conversion is applicatio s i for atio wu uu figure 9. internal serial clock, reduced data output length (1) (0) en sgl a2 a1 a0 odd/ sign sdi don? care don? care sdo sck (internal) cs >t eoctest msb sig bit 8 test eoc (optional) test eoc bit 27 bit 26 bit 25 bit 24 bit 28 bit 29 bit 30 eoc bit 31 eoc bit 0 sleep sleep data output hi-z hi-z hi-z hi-z hi-z data output conversion conversion sleep 2411 f09 LTC2418 4-wire spi interface
ltc2414/LTC2418 24 241418f complete, sck and sdo go low (eoc = 0) indicating the conversion has finished and the device has entered the low power sleep state. the part remains in the sleep state a minimum amount of time (1/2 the internal sck period) then immediately begins outputting data. the data input/ output cycle begins on the first rising edge of sck and ends after the 32nd rising edge. the input data is then shifted in via the sdi pin on the rising edge of sck (including the first rising edge) and the output data is shifted out of the sdo pin on each falling edge of sck. the internally generated serial clock is output to the sck pin. this signal may be used to shift the conversion result into external circuitry. eoc can be latched on the first rising edge of sck and the last bit of the conversion result can be latched on the 32nd rising edge of sck. after the 32nd rising edge, sdo goes high (eoc = 1) indicating a new conversion is in progress. sck remains high during the conversion. preserving the converter accuracy the ltc2414/LTC2418 are designed to reduce as much as possible the conversion result sensitivity to device decoupling, pcb layout, antialiasing circuits, line fre- quency perturbations and so on. nevertheless, in order to preserve the extreme accuracy capability of this part, some simple precautions are desirable. digital signal levels the ltc2414/LTC2418s digital interface is easy to use. its digital inputs (sdi, f o , cs and sck in external sck mode of operation) accept standard ttl/cmos logic levels and the internal hysteresis receivers can tolerate edge rates as slow as 100 m s. however, some considerations are required to take advantage of the exceptional accuracy and low supply current of this converter. the digital output signals (sdo and sck in internal sck mode of operation) are less of a concern because they are not generally active during the conversion state. while a digital input signal is in the range 0.5v to (v cc C 0.5v), the cmos input receiver draws additional current from the power supply. it should be noted that, when any one of the digital input signals (sdi, f o , cs and sck in external sck mode of operation) is within this range, the power supply current may increase even if the signal in question is at a valid logic level. for micropower applicatio s i for atio wu uu figure 10. internal serial clock, cs = 0 continuous operation (1) (0) en sgl a2 a1 a0 odd/ sign sdi don? care don? care sdo sck (internal) cs lsb msb sig bit 6 bit 0 parity bit 27 bit 26 bit 25 bit 24 bit 28 bit 29 bit 30 eoc bit 31 data output conversion conversion 241418 f10 v cc f o ref + ref ch0 ch7 ch8 ch15 com sck sdi sdo cs gnd 920 11 12 21 28 1 8 10 18 17 15 16 19 reference voltage 0.1v to v cc analog inputs = 50hz rejection = external oscillator = 60hz rejection v cc 1 f 2.7v to 5.5v ltc2414/ LTC2418 3-wire spi interface
ltc2414/LTC2418 25 241418f operation, it is recommended to drive all digital input signals to full cmos levels [v il < 0.4v and v oh > (v cc C 0.4v)]. during the conversion period, the undershoot and/or overshoot of a fast digital signal connected to the pins may severely disturb the analog to digital conversion process. undershoot and overshoot can occur because of the impedance mismatch at the converter pin when the transition time of an external control signal is less than twice the propagation delay from the driver to ltc2414/ LTC2418. for reference, on a regular fr-4 board, signal propagation velocity is approximately 183ps/inch for internal traces and 170ps/inch for surface traces. thus, a driver generating a control signal with a minimum transi- tion time of 1ns must be connected to the converter pin through a trace shorter than 2.5 inches. this problem becomes particularly difficult when shared control lines are used and multiple reflections may occur. the solution is to carefully terminate all transmission lines close to their characteristic impedance. parallel termination near the ltc2414/LTC2418 pin will eliminate this problem but will increase the driver power dissipation. a series resistor between 27 w and 56 w placed near the driver or near the ltc2414/LTC2418 pin will also eliminate this problem without additional power dissipation. the actual resistor value depends upon the trace impedance and connection topology. an alternate solution is to reduce the edge rate of the control signals. it should be noted that using very slow edges will increase the converter power supply current during the transition time. the differential input and refer- ence architecture reduce substantially the converters sensitivity to ground currents. particular attention must be given to the connection of the f o signal when the ltc2414/LTC2418 are used with an external conversion clock. this clock is active during the conversion time and the normal mode rejection provided by the internal digital filter is not very high at this fre- quency. a normal mode signal of this frequency at the converter reference terminals may result into dc gain and inl errors. a normal mode signal of this frequency at the converter input terminals may result into a dc offset error. applicatio s i for atio wu uu such perturbations may occur due to asymmetric capaci- tive coupling between the f o signal trace and the converter input and/or reference connection traces. an immediate solution is to maintain maximum possible separation between the f o signal trace and the input/reference sig- nals. when the f o signal is parallel terminated near the converter, substantial ac current is flowing in the loop formed by the f o connection trace, the termination and the ground return path. thus, perturbation signals may be inductively coupled into the converter input and/or refer- ence. in this situation, the user must reduce to a minimum the loop area for the f o signal as well as the loop area for the differential input and reference connections. driving the input and reference the input and reference pins of the ltc2414/LTC2418 converters are directly connected to a network of sampling capacitors. depending upon the relation between the differential input voltage and the differential reference voltage, these capacitors are switching between these four pins transferring small amounts of charge in the process. a simplified equivalent circuit is shown in figure 11. for a simple approximation, the source impedance r s driving an analog input pin (in + , in C , ref + or ref C ) can be considered to form, together with r sw and c eq (see figure 11), a first order passive network with a time constant t = (r s + r sw ) ? c eq . the converter is able to sample the input signal with better than 1ppm accuracy if the sampling period is at least 14 times greater than the input circuit time constant t . the sampling process on the four input analog pins is quasi-independent so each time constant should be considered by itself and, under worst- case circumstances, the errors may add. when using the internal oscillator (f o = low or high), the ltc2414/LTC2418s front-end switched-capacitor net- work is clocked at 76800hz corresponding to a 13 m s sampling period. thus, for settling errors of less than 1ppm, the driving source impedance should be chosen such that t 13 m s/14 = 920ns. when an external oscillator of frequency f eosc is used, the sampling period is 2/f eosc and, for a settling error of less than 1ppm, t 0.14/f eosc .
ltc2414/LTC2418 26 241418f input current if complete settling occurs on the input, conversion re- sults will be unaffected by the dynamic input current. an incomplete settling of the input signal sampling process may result in gain and offset errors, but it will not degrade the inl performance of the converter. figure 11 shows the mathematical expressions for the average bias currents flowing through the in + and in C pins as a result of the sampling charge transfers when integrated over a sub- stantial time period (longer than 64 internal clock cycles). the effect of this input dynamic current can be analyzed using the test circuit of figure 12. the c par capacitor includes the ltc2414/LTC2418 pin capacitance (5pf typi- cal) plus the capacitance of the test fixture used to obtain the results shown in figures 13 and 14. a careful imple- mentation can bring the total input capacitance (c in + c par ) closer to 5pf thus achieving better performance than the one predicted by figures 13 and 14. for simplic- ity, two distinct situations can be considered. for relatively small values of input capacitance (c in < 0.01 m f), the voltage on the sampling capacitor settles almost completely and relatively large values for the applicatio s i for atio wu uu source impedance result in only small errors. such values for c in will deteriorate the converter offset and gain performance without significant benefits of signal filtering and the user is advised to avoid them. nevertheless, when small values of c in are unavoidably present as parasitics of input multiplexers, wires, connectors or sensors, the ltc2414/LTC2418 can maintain its exceptional accuracy while operating with relative large values of source resis- tance as shown in figures 13 and 14. these measured results may be slightly different from the first order approximation suggested earlier because they include the effect of the actual second order input network together with the nonlinear settling process of the input amplifiers. for small c in values, the settling on in + and in C occurs almost independently and there is little benefit in trying to match the source impedance for the two pins. larger values of input capacitors (c in > 0.01 m f) may be required in certain configurations for antialiasing or gen- eral input signal filtering. such capacitors will average the input sampling charge and the external source resistance will see a quasi constant input differential impedance. when f o = low (internal oscillator and 60hz notch), the v ref + v in + v cc r sw (typ) 20k i leak i leak v cc i leak i leak v cc r sw (typ) 20k c eq 18pf (typ) r sw (typ) 20k i leak i in + v in i in i ref + i ref 2414/18 f11 i leak v cc i leak i leak switching frequency f sw = 76800hz internal oscillator (f o = low or high) f sw = 0.5 ?f eosc external oscillator v ref r sw (typ) 20k figure 11. ltc2414/LTC2418 equivalent analog input circuit iin vv v r iin vv v r iref vv v r v vr iref vv v r v vr where avg in incm refcm eq avg in incm refcm eq avg ref incm refcm eq in ref eq avg ref incm refcm eq in ref eq + - + - () = +- () = -+ - () = - + - () = - - + + 05 05 15 05 15 05 2 2 . . . . . . :: . . ./ v ref ref v ref ref vinin v in in r m internal oscillator hz notch f low r m internal oscillator hz notch f high r f external oscillator ref refcm in incm eq o eq o eq eosc =- = + ? ? ? ? =- = - ? ? ? ? == () == () = () +- +- +- +- 2 2 361 60 432 50 0 555 10 12 w w
ltc2414/LTC2418 27 241418f c in 2414/18 f12 v incm + 0.5v in r source in + ltc2414/ LTC2418 c par @ 20pf c in v incm ?0.5v in r source in c par @ 20pf r source ( ) 1 10 100 1k 10k 100k +fs error (ppm of v ref ) 2414/18 f13 50 40 30 20 10 0 v cc = 5v ref + = 5v ref = gnd in + = 3.75v in = 1.25v f o = gnd t a = 25 c c in = 0.01 f c in = 0.001 f c in = 100pf c in = 0pf r source ( ) 1 10 100 1k 10k 100k fs error (ppm of v ref ) 2414/18 f14 0 ?0 ?0 ?0 ?0 ?0 v cc = 5v ref + = 5v ref = gnd in + = 1.25v in = 3.75v f o = gnd t a = 25 c c in = 0.01 f c in = 0.001 f c in = 100pf c in = 0pf figure 12. an rc netwrk at in + and in C figure 13. +fs error vs r source at in + or in C (small c in ) figure 14. Cfs error vs r source at in + or in C (small c in ) applicatio s i for atio wu uu typical differential input resistance is 1.8m w which will generate a gain error of approximately 0.28ppm for each ohm of source resistance driving in + or in C . when f o = high (internal oscillator and 50hz notch), the typical differential input resistance is 2.16m w which will generate a gain error of approximately 0.23ppm for each ohm of source resistance driving in + or in C . when f o is driven by an external oscillator with a frequency f eosc (external conversion clock operation), the typical differential input resistance is 0.28 ? 10 12 /f eosc w and each ohm of source resistance driving in + or in C will result in 1.78 ? 10 C6 ? f eosc ppm gain error. the effect of the source resistance on the two input pins is additive with respect to this gain error. the typical +fs and Cfs errors as a function of the sum of the source resistance seen by in + and in C for large values of c in are shown in figures 15 and 16. in addition to this gain error, an offset error term may also appear. the offset error is proportional with the mismatch between the source impedance driving the two input pins in + and in C and with the difference between the input and reference common mode voltages. while the input drive circuit nonzero source impedance combined with the converter average input current will not degrade the inl performance, indirect distortion may result from the modu- lation of the offset error by the common mode component of the input signal. thus, when using large c in capacitor values, it is advisable to carefully match the source imped- ance seen by the in + and in C pins. when f o = low (internal oscillator and 60hz notch), every 1 w mismatch in source impedance transforms a full-scale common mode input signal into a differential mode input signal of 0.28ppm. when f o = high (internal oscillator and 50hz notch), every 1 w mismatch in source impedance transforms a full-scale common mode input signal into a differential mode input signal of 0.23ppm. when f o is driven by an external oscillator with a frequency f eosc , every 1 w mismatch in source impedance transforms a full-scale common mode input signal into a differential mode input signal of
ltc2414/LTC2418 28 241418f r source ( ) 0 100 200 300 400 500 600 700 800 900 1000 +fs error (ppm of v ref ) 2414/18 f15 300 240 180 120 60 0 v cc = 5v ref + = 5v ref = gnd in + = 3.75v in = 1.25v f o = gnd t a = 25 c c in = 0.01 f c in = 0.1 f c in = 1 f, 10 f r source ( ) 0 100 200 300 400 500 600 700 800 900 1000 fs error (ppm of v ref ) 2414/18 f16 0 ?0 120 180 240 300 v cc = 5v ref + = 5v ref = gnd in + = 1.25v in = 3.75v f o = gnd t a = 25 c c in = 0.01 f c in = 0.1 f c in = 1 f, 10 f v incm (v) 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 offset error (ppm of v ref ) 2414/18 f17 120 100 80 60 40 20 0 ?0 ?0 ?0 ?0 100 120 f o = gnd t a = 25 c r sourcein ?= 500 c in = 10 f v cc = 5v ref + = 5v ref = gnd in + = in = v incm a: ? r in = +400 b: ? r in = +200 c: ? r in = +100 d: ? r in = 0 e: ? r in = 100 f: ? r in = 200 g: ? r in = 400 a b c d e f g figure 15. +fs error vs r source at in + or in C (large c in ) figure 16. Cfs error vs r source at in + or in C (large c in ) figure 17. offset error vs common mode voltage (v incm = in + = in C ) and input source resistance imbalance ( d r in = r sourcein + C r sourcein C) for large c in values (c in 3 1 m f) applicatio s i for atio wu uu 1.78 ? 10 C6 ? f eosc ppm. figure 17 shows the typical offset error due to input common mode voltage for various values of source resistance imbalance between the in + and in C pins when large c in values are used. if possible, it is desirable to operate with the input signal common mode voltage very close to the reference signal common mode voltage as is the case in the ratiometric measurement of a symmetric bridge. this configuration eliminates the offset error caused by mismatched source impedances. the magnitude of the dynamic input current depends upon the size of the very stable internal sampling capacitors and upon the accuracy of the converter sampling clock. the accuracy of the internal clock over the entire temperature and power supply range is typical better than 0.5%. such a specification can also be easily achieved by an external clock. when relatively stable resistors (50ppm/ c) are used for the external source impedance seen by in + and in C , the expected drift of the dynamic current, offset and gain errors will be insignificant (about 1% of their respec- tive values over the entire temperature and voltage range). even for the most stringent applications, a one-time calibration operation may be sufficient. in addition to the input sampling charge, the input esd protection diodes have a temperature dependent leakage current. this current, nominally 1na ( 10na max), results in a small offset shift. a 100 w source resistance will create a 0.1 m v typical and 1 m v maximum offset voltage. reference current in a similar fashion, the ltc2414/LTC2418 samples the differential reference pins ref + and ref C transferring small amount of charge to and from the external driving circuits thus producing a dynamic reference current. this current does not change the converter offset, but it may degrade the gain and inl performance. the effect of this current can be analyzed in the same two distinct situa- tions. for relatively small values of the external reference capaci- tors (c ref < 0.01 m f), the voltage on the sampling capacitor settles almost completely and relatively large values for the source impedance result in only small errors. such
ltc2414/LTC2418 29 241418f values for c ref will deteriorate the converter offset and gain performance without significant benefits of reference filtering and the user is advised to avoid them. larger values of reference capacitors (c ref > 0.01 m f) may be required as reference filters in certain configurations. such capacitors will average the reference sampling charge and the external source resistance will see a quasi con- stant reference differential impedance. when f o = low (internal oscillator and 60hz notch), the typical differential reference resistance is 1.3m w which will generate a gain error of approximately 0.38ppm for each ohm of source resistance driving ref + or ref C . when f o = high (internal oscillator and 50hz notch), the typical differential refer- ence resistance is 1.56m w which will generate a gain error applicatio s i for atio wu uu r source ( ) 1 10 100 1k 10k 100k +fs error (ppm of v ref ) 2414/18 f18 0 ?0 ?0 ?0 ?0 ?0 v cc = 5v ref + = 5v ref = gnd in + = 3.75v in = 1.25v f o = gnd t a = 25 c c ref = 0.01 f c ref = 0.001 f c ref = 100pf c ref = 0pf r source ( ) 1 10 100 1k 10k 100k fs error (ppm of v ref ) 2414/18 f19 50 40 30 20 10 0 v cc = 5v ref + = 5v ref = gnd in + = 1.25v in = 3.75v f o = gnd t a = 25 c c ref = 0.01 f c ref = 0.001 f c ref = 100pf c ref = 0pf r source ( ) 0 100 200 300 400 500 600 700 800 900 1000 +fs error (ppm of v ref ) 2414/18 f20 0 ?0 180 270 360 450 v cc = 5v ref + = 5v ref = gnd in + = 3.75v in = 1.25v f o = gnd t a = 25 c c ref = 0.01 f c ref = 0.1 f c ref = 1 f, 10 f r source ( ) 0 100 200 300 400 500 600 700 800 900 1000 fs error (ppm of v ref ) 2414/18 f21 450 360 270 180 90 0 v cc = 5v ref + = 5v ref = gnd in + = 1.25v in = 3.75v f o = gnd t a = 25 c c ref = 0.01 f c ref = 0.1 f c ref = 1 f, 10 f figure 18. +fs error vs r source at ref + or ref C (small c in ) figure 19. Cfs error vs r source at ref + or ref C (small c in ) figure 20. +fs error vs r source at ref + and ref C (large c ref ) figure 21. Cfs error vs r source at ref + and ref C (large c ref ) of approximately 0.32ppm for each ohm of source resis- tance driving ref + or ref C . when f o is driven by an external oscillator with a frequency f eosc (external conver- sion clock operation), the typical differential reference resistance is 0.20 ? 10 12 /f eosc w and each ohm of source resistance driving ref + or ref C will result in 2.47 ? 10 C6 ? f eosc ppm gain error. the effect of the source resistance on the two reference pins is additive with respect to this gain error. the typical +fs and Cfs errors for various combinations of source resistance seen by the ref + and ref C pins and external capacitance c ref con- nected to these pins are shown in figures 18, 19, 20 and 21.
ltc2414/LTC2418 30 241418f in addition to this gain error, the converter inl perfor- mance is degraded by the reference source impedance. when f o = low (internal oscillator and 60hz notch), every 100 w of source resistance driving ref + or ref C translates into about 1.34ppm additional inl error. when f o = high (internal oscillator and 50hz notch), every 100 w of source resistance driving ref + or ref C translates into about 1.1ppm additional inl error. when f o is driven by an external oscillator with a frequency f eosc , every 100 w of source resistance driving ref + or ref C translates into about 8.73 ? 10 C6 ? f eosc ppm additional inl error. figure 22 shows the typical inl error due to the source resistance driving the ref + or ref C pins when large c ref values are used. the effect of the source resistance on the two reference pins is additive with respect to this inl error. in general, matching of source impedance for the ref + and ref C pins does not help the gain or the inl error. the user is thus advised to minimize the combined source impedance driving the ref + and ref C pins rather than to try to match it. the magnitude of the dynamic reference current depends upon the size of the very stable internal sampling capaci- tors and upon the accuracy of the converter sampling clock. the accuracy of the internal clock over the entire temperature and power supply range is typical better than 0.5%. such a specification can also be easily achieved by an external clock. when relatively stable resistors (50ppm/ c) are used for the external source impedance seen by ref + and ref C , the expected drift of the dynamic current gain error will be insignificant (about 1% of its value over the entire temperature and voltage range). even for the most stringent applications a onetime calibration operation may be sufficient. in addition to the reference sampling charge, the reference pins esd protection diodes have a temperature dependent leakage current. this leakage current, nominally 1na ( 10na max), results in a small gain error. a 100 w source resistance will create a 0.05 m v typical and 0.5 m v maxi- mum full-scale error. output data rate when using its internal oscillator, the ltc2414/LTC2418 can produce up to 7.5 readings per second with a notch frequency of 60hz (f o = low) and 6.25 readings per second with a notch frequency of 50hz (f o = high). the actual output data rate will depend upon the length of the sleep and data output phases which are controlled by the user and which can be made insignificantly short. when operated with an external conversion clock (f o connected to an external oscillator), the ltc2414/LTC2418 output data rate can be increased as desired up to that determined by the maximum f eosc frequency of 2000khz. the dura- tion of the conversion phase is 20510/f eosc . if f eosc = 153600hz, the converter behaves as if the internal oscil- lator is used and the notch is set at 60hz. there is no significant difference in the ltc2414/LTC2418 perfor- mance between these two operation modes. an increase in f eosc over the nominal 153600hz will translate into a proportional increase in the maximum output data rate. this substantial advantage is neverthe- less accompanied by three potential effects, which must be carefully considered. first, a change in f eosc will result in a proportional change in the internal notch position and in a reduction of the converter differential mode rejection at the power line frequency. in many applications, the subsequent perfor- mance degradation can be substantially reduced by rely- ing upon the ltc2414/LTC2418s exceptional common applicatio s i for atio wu uu figure 22. inl vs differential input voltage (v in = in + C in C ) and reference source resistance (r source at ref + and ref C for large c ref values (c ref 3 1 m f) v indif /v refdif ?.5 0.40.30.20.1 0 0.1 0.2 0.3 0.4 0.5 inl (ppm of v ref ) 15 12 9 6 3 0 ? ? ? ?2 ?5 v cc = 5v ref+ = 5v ref?= gnd v incm = 0.5 ?(in + + in ) = 2.5v f o = gnd c ref = 10 f t a = 25 c r source = 1000 r source = 500 r source = 100 2414/18 f22
ltc2414/LTC2418 31 241418f mode rejection and by carefully eliminating common mode to differential mode conversion sources in the input circuit. the user should avoid single-ended input filters and should maintain a very high degree of matching and symmetry in the circuits driving the in + and in C pins. second, the increase in clock frequency will increase proportionally the amount of sampling charge transferred through the input and the reference pins. if large external input and/or reference capacitors (c in , c ref ) are used, the previous section provides formulae for evaluating the effect of the source resistance upon the converter perfor- mance for any value of f eosc . if small external input and/ or reference capacitors (c in , c ref ) are used, the effect of the external source resistance upon the ltc2414/LTC2418 typical performance can be inferred from figures 12, 13, 18 and 19 in which the horizontal axis is scaled by 153600/ f eosc . third, an increase in the frequency of the external oscilla- tor above 460800hz (a more than 3 increase in the output data rate) will start to decrease the effectiveness of the internal autocalibration circuits. this will result in a progressive degradation in the converter accuracy and linearity. typical measured performance curves for output data rates up to 100 readings per second are shown in figures 23, 24, 25, 26, 27, 28, 29 and 30. in order to obtain the highest possible level of accuracy from this converter at output data rates above 20 readings per second, the user is advised to maximize the power supply voltage used and to limit the maximum ambient operating temperature. in certain circumstances, a reduction of the differential reference voltage may be beneficial. input bandwidth the combined effect of the internal sinc 4 digital filter and of the analog and digital autocalibration circuits deter- mines the ltc2414/LTC2418 input bandwidth. when the internal oscillator is used with the notch set at 60hz (f o = low), the 3db input bandwidth is 3.63hz. when the internal oscillator is used with the notch set at 50hz (f o = high), the 3db input bandwidth is 3.02hz. if an external conversion clock generator of frequency f eosc is connected to the f o pin, the 3db input bandwidth is 0.236 ? 10 C6 ? f eosc . applicatio s i for atio wu uu output data rate (readings/sec) 200 160 120 80 40 0 ?0 ?0 ?20 ?60 ?00 offset error (ppm of v error ) 2414/18 f23 0 102030 40 50 60 70 80 90 100 t a = 25 c t a = 85 c v cc = 5v v ref = 5v v in = 2.5v v incm = 2.5v sdi = gnd f o = external oscillator output data rate (readings/sec) 0 +fs error (ppm of v ref ) 2000 0 ?000 4000 6000 8000 ?0000 ?2000 2414/18 f24 20 100 90 80 70 60 50 10 30 40 t a = 25 c t a = 85 c v cc = 5v v ref = 5v v in = 2.5v v incm = 2.5v sdi = gnd f o = external oscillator output data rate (readings/sec) 0 fs error (ppm of v ref ) 12000 10000 8000 6000 4000 2000 0 ?000 2414/18 f25 20 100 90 80 70 60 50 10 30 40 t a = 25 c t a = 85 c v cc = 5v v ref = 5v v in = 2.5v v incm = 2.5v sdi = gnd f o = external oscillator figure 23. offset error vs output data rate and temperature figure 24. +fs error vs output data rate and temperature figure 25. Cfs error vs output data rate and temperature
ltc2414/LTC2418 32 241418f figure 26. resolution (noise rms 1lsb) vs output data rate and temperature figure 27. resolution (inl rms 1lsb) vs output data rate and temperature figure 28. offset error vs output data rate and reference voltage figure 29. resolution (noise rms 1lsb) vs output data rate and reference voltage figure 30. resolution (inl max 1lsb) vs output data rate and reference voltage figure 31. input signal bandwidth using the internal oscillator applicatio s i for atio wu uu output data rate (readings/sec) 0 102030405060708090100 resolution (bits) 2414/18 f26 24 23 22 21 20 19 18 17 16 15 14 13 12 t a = 85 c v cc = 5v ref + = 5v ref = gnd v incm = 2.5v v in = 0v sdi = gnd f o = external oscillator resolution = log 2 (v ref /noise rms ) t a = 25 c output data rate (readings/sec) 0 102030405060708090100 resolution (bits) 2414/18 f27 22 20 18 16 14 12 10 8 t a = 85 c v cc = 5v ref + = 5v ref = gnd v incm = 2.5v ?.5v < v in < 2.5v sdi = gnd f o = external oscillator resolution = log 2 (v ref /inl max ) t a = 25 c output data rate (readings/sec) 200 150 100 50 0 ?0 offset error (ppm of v ref ) 2414/18 f28 0 102030 40 50 60 70 80 90 100 v ref = 5v v ref = 2.5v f o = external oscillator v cc = 5v ref ? = gnd v in = 0v v incm = 2.5v sdi = gnd t a = 25 c output data rate (readings/sec) 0 102030405060708090100 resolution (bits) 2414/18 f29 24 23 22 21 20 19 18 17 16 15 14 13 12 v ref = 5v v cc = 5v ref = gnd v incm = 2.5v v in = 0v sdi = gnd f o = external oscillator t a = 25 c resolution = log 2 (v ref /noise rms ) v ref = 2.5v output data rate (readings/sec) 0 102030405060708090100 resolution (bits) 2414/18 f30 22 20 18 16 14 12 10 8 t a = 25 c v cc = 5v ref = gnd v incm = 0.5 ?ref + 0.5v ?v ref < v in < 0.5 ?v ref sdi = gnd f o = external oscillator v ref = 2.5v v ref = 5v resolution = log 2 (v ref /inl max ) differential input signal frequency (hz) 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 input signal attenuation (db) 2414/18 f31 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 f o = high f o = low due to the complex filtering and calibration algorithms utilized, the converter input bandwidth is not modeled very accurately by a first order filter with the pole located at the 3db frequency. when the internal oscillator is used, the shape of the ltc2414/LTC2418 input bandwidth is shown in figure 31 for f o = low and f o = high. when an external oscillator of frequency f eosc is used, the shape of the ltc2414/LTC2418 input bandwidth can be derived from figure 31, f o = low curve in which the horizontal axis is scaled by f eosc /153600. the conversion noise (1 m v rms typical for v ref = 5v) can be modeled by a white noise source connected to a noise free converter. the noise spectral density is 78nv/ ? hz for an infinite bandwidth source and 107nv/ ? hz for a single 0.5mhz pole source. from these numbers, it is clear that particular attention must be given to the design of external amplification circuits. such circuits face the simultaneous requirements of very low bandwidth (just a few hz) in order to reduce the output referred noise and relatively high bandwidth (at least 500khz) necessary to drive the input switched-capacitor network. a possible solution is a high gain, low bandwidth amplifier stage followed by a high bandwidth unity-gain buffer.
ltc2414/LTC2418 33 241418f applicatio s i for atio wu uu when external amplifiers are driving the ltc2414/ LTC2418, the adc input referred system noise calculation can be simplified by figure 32. the noise of an amplifier driving the ltc2414/LTC2418 input pin can be modeled as a band limited white noise source. its bandwidth can be approximated by the bandwidth of a single pole lowpass filter with a corner frequency f i . the amplifier noise spec- tral density is n i . from figure 32, using f i as the x-axis selector, we can find on the y-axis the noise equivalent bandwidth freq i of the input driving amplifier. this band- width includes the band limiting effects of the adc internal calibration and filtering. the noise of the driving amplifier referred to the converter input and including all these effects can be calculated as n = n i ? ? freq i . the total system noise (referred to the ltc2414/LTC2418 input) can now be obtained by summing as square root of sum of squares the three adc input referred noise sources: the ltc2414/ LTC2418 internal noise (1 m v), the noise of the in + driving amplifier and the noise of the in C driving amplifier. if the f o pin is driven by an external oscillator of frequency f eosc , figure 32 can still be used for noise calculation if the x-axis is scaled by f eosc /153600. for large values of the ratio f eosc /153600, the figure 32 plot accuracy begins to decrease, but in the same time the ltc2414/LTC2418 noise floor rises and the noise contribution of the driving amplifiers lose significance. normal mode rejection and antialiasing one of the advantages delta-sigma adcs offer over con- ventional adcs is on-chip digital filtering. combined with a large oversampling ratio, the ltc2414/LTC2418 signifi- cantly simplify antialiasing filter requirements. the sinc 4 digital filter provides greater than 120db normal mode rejection at all frequencies except dc and integer multiples of the modulator sampling frequency (f s ). the ltc2414/LTC2418s autocalibration circuits further sim- plify the antialiasing requirements by additional normal mode signal filtering both in the analog and digital domain. independent of the operating mode, f s = 256 ? f n = 2048 ? f outmax where f n in the notch frequency and f outmax is the maximum output data rate. in the internal oscillator mode with a 50hz notch setting, f s = 12800hz and with a 60hz notch setting f s = 15360hz. in the external oscillator mode, f s = f eosc /10. figure 33. input normal mode rejection, internal oscillator and 50hz notch figure 34. input normal mode rejection, internal oscillator and 60hz notch or external oscillator figure 32. input referred noise equivalent bandwidth of an input connected white noise source input noise source single pole equivalent bandwidth (hz) 1 input referred noise equivalent bandwidth (hz) 10 0.1 1 10 100 1k 10k 100k 1m 2414/18 f32 0.1 100 f o = high f o = low differential input signal frequency (hz) 0f s 2f s 3f s 4f s 5f s 6f s 7f s 8f s 9f s 10f s 11f s 12f s input normal mode rejection (db) 2414/18 f33 0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 100 110 120 f o = high f o = low or f o = external oscillator, f eosc = 10 ?f s differential input signal frequency (hz) 0f s input normal mode rejection (db) 2414/18 f34 0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 100 110 120 2f s 3f s 4f s 5f s 6f s 7f s 8f s 9f s 10f s
ltc2414/LTC2418 34 241418f the combined normal mode rejection performance is shown in figure 33 for the internal oscillator with 50hz notch setting (f o = high) and in figure 34 for the internal oscillator with 60hz notch setting (f o = low) and for the external oscillator mode. the regions of low rejection occurring at integer multiples of f s have a very narrow bandwidth. magnified details of the normal mode rejection curves are shown in figure 35 (rejection near dc) and figure 36 (rejection at f s = 256f n ) where f n represents the notch frequency. these curves have been derived for the external oscillator mode but they can be used in all operating modes by appropriately selecting the f n value. the user can expect to achieve in practice this level of performance using the internal oscillator as it is demon- strated by figures 37 and 38. typical measured values of the normal mode rejection of the ltc2414/LTC2418 operating with an internal oscillator and a 60hz notch setting are shown in figure 37 superimposed over the theoretical calculated curve. similarly, typical measured values of the normal mode rejection of the ltc2414/ LTC2418 operating with an internal oscillator and a 50hz notch setting are shown in figure 38 superimposed over the theoretical calculated curve. as a result of these remarkable normal mode specifica- tions, minimal (if any) antialias filtering is required in front of the ltc2414/LTC2418. if passive rc components are placed in front of the ltc2414/LTC2418, the input dy- namic current should be considered (see input current section). in cases where large effective rc time constants are used, an external buffer amplifier may be required to minimize the effects of dynamic input current. figure 35. input normal mode rejection figure 36. input normal mode rejection figure 37. input normal mode rejection vs input frequency with input perturbation of 100% full scale (60hz notch) figure 38. input normal mode rejection vs input frequency with input perturbation of 100% full scale (50hz notch) applicatio s i for atio wu uu input signal frequency (hz) input normal mode rejection (db) 2414/18 f35 0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 100 110 120 f n 0 2f n 3f n 4f n 5f n 6f n 7f n 8f n input signal frequency (hz) 250f n 252f n 254f n 256f n 258f n 260f n 262f n input normal mode rejection (db) 2414/18 f36 0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 100 110 120 input frequency (hz) 0 15 30 45 60 75 90 105 120 135 150 165 180 195 210 225 240 normal mode rejection (db) 2414/18 f37 0 ?0 ?0 ?0 ?0 100 120 v cc = 5v ref + = 5v ref = gnd v incm = 2.5v v in(p-p) = 5v sdi = gnd f o = gnd t a = 25 c measured data calculated data input frequency (hz) 0 12.5 25 37.5 50 62.5 75 87.5 100 112.5 125 137.5 150 162.5 175 187.5 200 normal mode rejection (db) 2414/18 f38 0 ?0 ?0 ?0 ?0 100 120 v cc = 5v ref + = 5v ref = gnd v incm = 2.5v v in(p-p) = 5v sdi = gnd f o = 5v t a = 25 c measured data calculated data
ltc2414/LTC2418 35 241418f traditional high order delta-sigma modulators, while providing very good linearity and resolution, suffer from potential instabilities at large input signal levels. the pro- prietary architecture used for the ltc2414/LTC2418 third order modulator resolves this problem and guarantees a predictable stable behavior at input signal levels of up to 150% of full scale. in many industrial applications, it is not uncommon to have to measure microvolt level signals superimposed over volt level perturbations and ltc2414/ LTC2418 is eminently suited for such tasks. when the perturbation is differential, the specification of interest is the normal mode rejection for large input signal levels. with a reference voltage v ref = 5v, the ltc2414/LTC2418 has a full-scale differential input range of 5v peak-to-peak. figures 39 and 40 show measurement results for the ltc2414/LTC2418 normal mode rejection ratio with a 7.5v peak-to-peak (150% of full scale) input signal superim- posed over the more traditional normal mode rejection ratio results obtained with a 5v peak-to-peak (full scale) input signal. in figure 39, the ltc2414/LTC2418 uses the internal oscillator with the notch set at 60hz (f o = low) and in figure 40 it uses the internal oscillator with the notch set at 50hz (f o = high). it is clear that the ltc2414/ LTC2418 rejection performance is maintained with no com- promises in this extreme situation. when operating with large input signal levels, the user must observe that such signals do not violate the device absolute maximum ratings. figure 39. measured input normal mode rejection vs input frequency with input perturbation of 150% full scale (60hz notch) figure 40. measured input normal mode rejection vs input frequency with input perturbation of 150% full scale (50hz notch) input frequency (hz) 0 15 30 45 60 75 90 105 120 135 150 165 180 195 210 225 240 normal mode rejection (db) 2414/18 f39 0 ?0 ?0 ?0 ?0 100 120 v cc = 5v ref + = 5v ref = gnd v incm = 2.5v sdi = gnd f o = gnd t a = 25 c v in(p-p) = 5v v in(p-p) = 7.5v (150% of full scale) input frequency (hz) 0 normal mode rejection (db) 2414/18 f40 0 ?0 ?0 ?0 ?0 100 120 v cc = 5v ref + = 5v ref = gnd v incm = 2.5v sdi = gnd f o = 5v t a = 25 c v in(p-p) = 5v v in(p-p) = 7.5v (150% of full scale) 12.5 25 37.5 50 62.5 75 87.5 100 112.5 125 137.5 150 162.5 175 187.5 200 applicatio s i for atio wu uu
ltc2414/LTC2418 36 241418f bridge applications typical strain gauge based bridges deliver only 2mv/volt of excitation. as the maximum reference voltage of the ltc2414/LTC2418 is 5v, remote sensing of applied exci- tation without additional circuitry requires that excitation be limited to 5v. this gives only 10mv full scale input signal, which can be resolved to 1 part in 10000 without averaging. for many solid state sensors, this is still better than the sensor. averaging 64 samples however reduces the noise level by a factor of eight, bringing the resolving power to 1 part in 80000, comparable to better weighing systems. hysteresis and creep effects in the load cells are typically much greater than this. most applications that require strain measurements to this level of accuracy are measuring slowly changing phenomena, hence the time required to average a large number of readings is usually not an issue. for those systems that require accurate measurement of a small incremental change on a signifi- cant tare weight, the lack of history effects in the ltc2400 family is of great benefit. for those applications that cannot be fulfilled by the ltc2414/LTC2418 alone, compensating for error in exter- nal amplification can be done effectively due to the no latency feature of the ltc2414/LTC2418. no latency operation allows samples of the amplifier offset and gain to be interleaved with weighing measurements. the use of correlated double sampling allows suppression of 1/f noise, offset and thermocouple effects within the bridge. correlated double sampling involves alternating the polar- ity of excitation and dealing with the reversal of input polarity mathematically. alternatively, bridge excitation can be increased to as much as 10v, if one of several precision attenuation techniques is used to produce a precision divide operation on the reference signal. an- other option is the use of a reference within the 5v input range of the ltc2414/LTC2418 and developing excitation via fixed gain, or ltc1043 based voltage multiplication, along with remote feedback in the excitation amplifiers, as shown in figures 46 and 47. figure 41 shows an example of a simple bridge connec- tion. note that it is suitable for any bridge application where measurement speed is not of the utmost impor- tance. for many applications where large vessels are weighed, the average weight over an extended period of time is of concern and short term weight is not readily determined due to movement of contents, or mechanical resonance. often, large weighing applications involve load cells located at each load bearing point, the output of which can be summed passively prior to the signal pro- cessing circuitry, actively with amplification prior to the adc, or can be digitized via multiple adc channels and summed mathematically. the mathematical summation of the output of multiple ltc2414/LTC2418s provides the benefit of a root square reduction in noise. the low power consumption of the ltc2414/LTC2418 makes it attractive for multidrop communication schemes where the adc is located within the load-cell housing. ref + ref sdi sck sdo cs 20 18 17 16 ch0 ch1 gnd v cc f o 11 r1 12 350 bridge 21 22 2414/18 f41 15 9 19 ltc2414/ LTC2418 + r2 r1 and r2 can be used to increase tolerable ac component on ref signals lt1019 0.1 f 0.1 f 10 f figure 41. simple bridge connection a direct connection to a load cell is perhaps best incorpo- rated into the load-cell body, as minimizing the distance to the sensor largely eliminates the need for protection devices, rfi suppression and wiring. the ltc2414/ LTC2418 exhibits extremely low temperature dependent drift. as a result, exposure to external ambient tempera- ture ranges does not compromise performance. the in- corporation of any amplification considerably compli- cates thermal stability, as input offset voltages and cur- rents, temperature coefficient of gain settling resistors all become factors. applicatio s i for atio wu uu
ltc2414/LTC2418 37 241418f the circuit in figure 42 shows an example of a simple amplification scheme. this example produces a differen- tial output with a common mode voltage of 2.5v, as determined by the bridge. the use of a true three amplifier instrumentation amplifier is not necessary, as the ltc2414/ LTC2418 has common mode rejection far beyond that of most amplifiers. the ltc1051 is a dual autozero amplifier that can be used to produce a gain of 15 before its input referred noise dominates the ltc2414/LTC2418 noise. this example shows a gain of 34, that is determined by a feedback network built using a resistor array containing 8 individual resistors. the resistors are organized to opti- mize temperature tracking in the presence of thermal gradients. the second ltc1051 buffers the low noise input stage from the transient load steps produced during conversion. the gain stability and accuracy of this approach is very good, due to a statistical improvement in resistor match- ing. a gain of 34 may seem low, when compared to common practice in earlier generations of load-cell inter- faces, however the accuracy of the ltc2414/LTC2418 changes the rationale. achieving high gain accuracy and linearity at higher gains may prove difficult, while provid- ing little benefit in terms of noise reduction. at a gain of 100, the gain error that could result from typical open-loop gain of 160db is C1ppm, however, worst-case is at the minimum gain of 116db, giving a gain error of C158ppm. worst-case gain error at a gain of 34, is C54ppm. the use of the ltc1051a reduces the worst- case gain error to C33ppm. the advantage of gain higher than 34, then becomes dubious, as the input referred noise sees little improvement and gain accuracy is poten- tially compromised. note that this 4-amplifier topology has advantages over the typical integrated 3-amplifier instrumentation ampli- fier in that it does not have the high noise level common in the output stage that usually dominates when and instru- mentation amplifier is used at low gain. if this amplifier is used at a gain of 10, the gain error is only 10ppm and input refered noise is reduced to 0.1 m v rms . the buffer stages can also be configured to provide gain of up to 50 with high gain stability and linearity. 0.1 f 8 0.1 f 0.1 f ref + ref sdi sck sd0 cs 20 18 17 16 ch0 ch1 gnd v cc f o 11 5v ref 12 350 bridge 21 22 2414/18 f42 15 2 19 ltc2414/ LTC2418 rn1 = 5k 8 resistor array u1a, u1b, u2a, u2b = 1/2 ltc1051 + 3 2 8 4 u1a 4 5v + 6 5 rn1 1 16 15 2 611 7 1 14 3 710 4 13 89 512 u1b + 2 3 u2a 5v 1 + 6 5 u2b 7 figure 42. using autozero amplifiers to reduce input referred noise applicatio s i for atio wu uu
ltc2414/LTC2418 38 241418f figure 43 shows an example of a single amplifier used to produce single-ended gain. this topology is best used in applications where the gain setting resistor can be made to match the temperature coefficient of the strain gauges. if the bridge is composed of precision resistors, with only one or two variable elements, the reference arm of the bridge can be made to act in conjunction with the feedback resistor to determine the gain. if the feedback resistor is incorporated into the design of the load cell, using resis- tors which match the temperature coefficient of the load- cell elements, good results can be achieved without the need for resistors with a high degree of absolute accuracy. the common mode voltage in this case, is again a function of the bridge output. differential gain as used with a 350 w bridge is a v = (r1+ r2)/(r1+175 w ). common mode gain is half the differential gain. the maximum differential signal that can be used is 1/4 v ref , as opposed to 1/2 v ref in the 2-amplifier topology above. remote half bridge interface as opposed to full bridge applications, typical half bridge applications must contend with nonlinearity in the bridge output, as signal swing is often much greater. applications include rtds, thermistors and other resistive elements that undergo significant changes over their span. for single variable element bridges, the nonlinearity of the half bridge output can be eliminated completely; if the refer- ence arm of the bridge is used as the reference to the adc, as shown in figure 44. the ltc2414/LTC2418 can accept inputs up to 1/2 v ref . hence, the reference resistor r1 must be at least 2x the highest value of the variable resistor. in the case of 100 w platinum rtds, this would suggest a value of 800 w for r1. such a low value for r1 is not advisable due to self-heating effects. a value of 25.5k is shown for r1, reducing self-heating effects to acceptable levels for most sensors. applicatio s i for atio wu uu figure 43. bridge amplification using a single amplifier 0.1 f 5v ref + ref ch0 ch1 gnd v cc 11 3 2 4 6 7 12 350 bridge 21 22 2410 f49 15 9 ltc2414/ LTC2418 + ltc1050s8 5v 0.1 v r2 46.4k 20k 20k 175 1 f 10 f r1 4.99k () a v = 9.95 = r1 + r2 r1 + 175 + + 1 f + 2410 f50 ref + ref ch0 ch1 gnd v cc v s 2.7v to 5.5v 11 12 21 22 platinum 100 rtd r1 25.5k 0.1% 15 9 ltc2414/ LTC2418 figure 44. remote half bridge interface
ltc2414/LTC2418 39 241418f the basic circuit shown in figure 44 shows connections for a full 4-wire connection to the sensor, which may be located remotely. the differential input connections will reject induced or coupled 60hz interference, however, the reference inputs do not have the same rejection. if 60hz or other noise is present on the reference input, a low pass filter is recommended as shown in figure 45. note that you cannot place a large capacitor directly at the junction of r1 and r2, as it will store charge from the sampling process. a better approach is to produce a low pass filter decoupled from the input lines with a high value resistor (r3). the use of a third resistor in the half bridge, between the variable and fixed elements gives essentially the same result as the two resistor version, but has a few benefits. if, for example, a 25k reference resistor is used to set the excitation current with a 100 w rtd, the negative refer- ence input is sampling the same external node as the positive input and may result in errors if used with a long cable. for short cable applications, the errors may be acceptably low. if instead the single 25k resistor is re- placed with a 10k 5% and a 10k 0.1% reference resistor, the noise level introduced at the reference, at least at higher frequencies, will be reduced. a filter can be intro- duced into the network, in the form of one or more capacitors, or ferrite beads, as long as the sampling pulses are not translated into an error. the reference voltage is also reduced, but this is not undesirable, as it will decrease the value of the lsb, although, not the input referred noise level. the circuit shown in figure 45 shows a more rigorous example of figure 44, with increased noise suppression and more protection for remote applications. figure 46 shows an example of gain in the excitation circuit and remote feedback from the bridge. the ltc1043s provide voltage multiplication, providing 10v from a 5v reference with only 1ppm error. the amplifiers are used at unity gain and introduce very little error due to gain error or due to offset voltages. a 1 m v/ c offset voltage drift translates into 0.05ppm/ c gain error. simpler alterna- tives, with the amplifiers providing gain using resistor arrays for feedback, can produce results that are similar to bridge sensing schemes via attenuators. note that the amplifiers must have high open-loop gain or gain error will be a source of error. the fact that input offset voltage has relatively little effect on overall error may lead one to use low performance amplifiers for this application. note that the gain of a device such as an lf156, (25v/mv over temperature) will produce a worst-case error of C180ppm at a noise gain of 3, such as would be encountered in an inverting gain of 2, to produce C10v from a 5v reference. applicatio s i for atio wu uu figure 45. remote half bridge sensing with noise suppression on reference ref + ref ch1 gnd v cc 5v 11 12 22 2410 f51 15 9 ltc2414/ LTC2418 + ltc1050 5v platinum 100 rtd 560 r3 10k 5% r1 10k, 5% r2 10k 0.1% 1 f ch0 21 10k 10k
ltc2414/LTC2418 40 241418f 350 bridge 0.1 f 1 f 15v 15v 15v 38 14 7 4 13 12 11 10v 5v 15v u1 ltc1043 6 2 7 4 7 4 + ref + ref ch0 ch1 gnd v cc 11 12 21 22 15 2410 f52 9 5v ltc2414/ LTC2418 47 f 0.1 f 10v + 17 5 15 6 18 3 2 u2 ltc1043 1 f film 8 14 7 4 13 12 11 * * * 5v u2 ltc1043 17 10v 10v lt1236-5 1k 33 q1 2n3904 0.1 f 15v 15v 15v 3 6 2 + 1k 33 10v 10v q2 2n3906 *flying capacitors are 1 f film (mkp or equivalent) see ltc1043 data sheet for details on unused half of u1 ltc1150 ltc1150 20 200 20 200 0.1 f 10 f + figure 46. ltc1043 provides precise 4x reference for excitation voltages applicatio s i for atio wu uu the error associated with the 10v excitation would be C80ppm. hence, overall reference error could be as high as 130ppm, the average of the two. figure 47 shows a similar scheme to provide excitation using resistor arrays to produce precise gain. the circuit is configured to provide 10v and C5v excitation to the bridge, producing a common mode voltage at the input to the ltc2414/LTC2418 of 2.5v, maximizing the ac input range for applications where induced 60hz could reach amplitudes up to 2v rms .
ltc2414/LTC2418 41 241418f multiple channel usage the ltc2414/LTC2418 have up to sixteen input channels and this feature provides a very flexible and efficient solution in applications where more than one variable need to be measured. measurements of a ladder of sensors in industrial process, it is likely that a large group of real world phenomena need to be monitored where the speed is not critical. one example is the cracking towers in petroleum refineries where a group of temperature mea- surements need to be taken and related. this is done by passing an excitation current through a ladder of rtds. the configuration using a single LTC2418 to monitor up to eight rtds in differential mode is shown in figure 48. a high accuracy r1 is used to set the excitation current and the reference voltage. a larger value of 25k is selected to c1 0.1 f 15v 3 1 2 3 2 1 6 5 4 + ref + ref ch0 ch1 gnd v cc 11 12 21 22 15 2410 f53 9 ltc2414/ LTC2418 lt1236-5 rn1 10k 22 10v 350 bridge two elements varying rn1 10k q1 2n3904 1/2 lt1112 c2 0.1 f 15v ?v ?5v 15v 6 7 5 8 7 + rn1 10k rn1 is caddock t914 10k-010-02 q2, q3 2n3906 2 1/2 lt1112 rn1 10k 33 2 c3 47 f c1 0.1 f 5v 5v 8 4 20 20 + figure 47. use resistor arrays to provide precise matching in excitation amplifier reduce the self-heating effects. r1 can also be broken into two resistors, one 25k to set the excitation current and the other a high accuracy 1k resistor to set the reference voltage, assuming 100 w platinum rtds. this results in a reduced reference voltage and a reduced common mode difference between the reference and the input signal, which improves the conversion linearity and reduces total error. each input should be taken close to the related rtd to minimize the error caused by parasitic wire resistance. the interference on a signal transmission line from rtd to the LTC2418 is rejected due to the excellent common mode rejection and the digital lpf included in the LTC2418. it should be noted that the input source resistance of cho can have a maximum value of 800 w ? 8 = 6.4k, so the parasitic capacitance and resistance of the connection wires need to be minimized in order not to degrade the converter performance. applicatio s i for atio wu uu
ltc2414/LTC2418 42 241418f applicatio s i for atio wu uu 20 18 17 16 19 sdi sck sdo cs f o ref + ref ch0 ch1 ch2 ch3 ch14 ch15 11 12 21 22 23 24 7 8 gnd v cc LTC2418 5v 9 15 0.1 f r1 25k 0.1% pt2 100 rtd pt1 100 rtd pt8 100 rtd 2418 f48 10 f + 4-wire spi figure 48. measurement of a ladder of sensors using differential mode multichannel bridge digitizer and digital cold junction compensation the bridge application as shown in figures 41, 42, and 43 can be expanded to multiple bridge transducers. figure 54 shows the expansion for simple bridge measurement. also included is the temperature measurement. in figure 54, ch0 to ch13 are configured as differential to measure up to seven bridge transducers using the LTC2418. ch14 and ch15 are configured as single-ended. ch14 measures the thermocouple while ch15 measures the output of the cold junction sensor (diode, thermistor, etc.). the measured cold junction sensor output is then used to compensate the thermocouple output to find the absolute temperature. the final temperature value may then be used to compensate the temperature effects of the bridge transducers. sample driver for ltc2414/LTC2418 spi interface the ltc2414/LTC2418 have a simple 4-wire serial inter- face and it is easy to program microprocessors and microcontrollers to control the device. figure 49 shows the 4-wire spi connection between the ltc2414/LTC2418 and a pic16f84 microcontroller. the sample program for cc5x compiler in figure 50 can be used to program the pic16f84 to control the ltc2414/ LTC2418. it uses port b to interface with the device. the program begins by declaring variables and allocating four memory locations to store the 32-bit conversion result. in execution, it first initiates the port b to the proper spi configuration and prepares channel address. the ltc2414/LTC2418 is activated by setting the cs low. then the microcontroller waits until a logic low is de- tected on the data line, signifying end-of-conversion. after a low is detected, a subroutine is called to exchange data between the ltc2414/LTC2418 and the microcontroller. the main loop ends by setting cs high, ending the data output state. the performance of the ltc2414/LTC2418 can be verified using the demonstration board dc434a, see figure 51 for the schematic. this circuit uses the computers serial port to generate power and the spi digital signals necessary for starting a conversion and reading the result. it includes a sck sdi sdo cs 18 20 17 16 8 9 10 11 pic16f84 ltc2414/ LTC2418 rb2 rb3 rb4 rb5 2414/18 f49 figure 49. connecting the ltc2414/LTC2418 to a pic16f84 mcu using the spi serial interface labview tm application software program (see figure 52) which graphically captures the conversion results. it can be used to determine noise performance, stability and with an external source linearity. as exemplified in the sche- matic, the ltc2414/LTC2418 is extremely easy to use. this demonstration board and associated software is available by contacting linear technology. labview is a trademark of national instruments corporation
ltc2414/LTC2418 43 241418f // LTC2418 pic16f84 interface example // written for cc5x compiler // processor is pic16f84 running at 10 mhz #include <16f84.h> #include #pragma origin = 0x4 #pragma config |= 0x3fff, wdte=off,fosc=hs // global pin definitions: #pragma bit rx_pin @ portb.0 //input #pragma bit tx_pin @ portb.1 //output #pragma bit sck @ portb.2 //output #pragma bit sdi @ portb.3 //output #pragma bit sdo @ portb.4 //input #pragma bit cs_bar @ portb.5 //output // global variables uns8 result_3; // conversion result ms byte uns8 result_2; // .. uns8 result_1; // .. uns8 result_0; // conversion result ls byte void shiftbidir(char nextch); // function prototype void main( void) { intcon=0b00000000; // no interrupts trisa=0b00000000; // all porta pins outputs trisb=0b00010001; // according to definitions above char channel; // next channel to send while(1) { /* channel bit fields are 7:6, 10 always; 5, en; 4, sgl; 3, odd/sign; 2:0, addr */ channel = 0b10101000; // ch0,1 diff. cs_bar=0; // activate adc while(sdo==1) // test for end of conversion { // wait if conversion is not complete } shiftbidir(channel); // read adc, send next channel cs_bar = 1; // deactivate adc /* at this point global variables result 3,2,1 contain the 24 bit conversion result. variable result3 contains the corresponding channel information in the following fields: bits 7:6, 00 always, 5, en; 4, sgl; 3, odd/sign; 2:0, addr */ } // end of loop } // end of main figure 50. sample program in cc5x for pic16f84 applicatio s i for atio wu uu
ltc2414/LTC2418 44 241418f ////////// bidirectional shift routine for adc ////////// void shiftbidir(char nextch) { int i; for(i=0;i<2;i++) // send config bits 7:6, // ignore eoc/ and dmy bits { sdi=nextch.7; // put data on pin nextch = rl(nextch); // get next config bit ready sck=1; // clock high sck=0; // clock low } for(i=0;i<8;i++) // send config, read byte 3 { sdi=nextch.7; // put data on pin nextch = rl(nextch); // get next config bit ready result_3 = rl(result_3);// get ready to load lsb result_3.0 = sdo; // load lsb sck=1; // clock high sck=0; // clock low } for(i=0;i<8;i++) // read byte 2 { result_2 = rl(result_2);// get ready to load lsb result_2.0 = sdo; // load lsb sck=1; // clock high sck=0; // clock low } for(i=0;i<8;i++) // read byte 1 { result_1 = rl(result_1);// get ready to load lsb result_1.0 = sdo; // load lsb sck=1; // clock high sck=0; // clock low } result_0=0; // ensure bits 7:6 are zero for(i=0;i<6;i++) // read byte 0 { result_0 = rl(result_0);// get ready to load lsb result_0.0 = sdo; // load lsb sck=1; // clock high sck=0; // clock low } } figure 50. sample program in cc5x for pic16f84 (cont) applicatio s i for atio wu uu
ltc2414/LTC2418 45 241418f figure 51. demo board schematic 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 11 12 21 22 23 24 25 26 27 28 1 2 3 4 5 6 7 8 13 14 15 19 18 17 16 20 u5 LTC2418cgn com v cc v cc v cc v cc v cc v cc v cc v cc v cc v cc v cc ref+ ref ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 ch8 ch9 ch10 ch11 ch12 ch13 ch14 ch15 f o sck sdo cs sdi nc nc gnd 10 11 12 13 14 3 4 5 6 2 15 1 16 9 7 8 jp6 jmpr 1 6 2 7 3 8 4 9 5 p1 db9 ser a b c d e f g h clk inh sh/ld v cc qh qh gnd + + + c5 10 f 35v jp5 jmpr c6 0.1 f c7 0.1 f c8 0.1 f e3 e4 gnd gnd gnd gnd ref ref + vex 50hz/60hz 1 2 3 1 1 2 2 3 1 2 3 1 2 3 banana jack j1 j2 j3 j4 p2 con40a 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 u4 74hc165 q1 mmbt3904lt1 r7 22k r8 51k r6 3k r4 51k r3 51k r5 49.9 2.5v 5v v out v in gnd u1 lt1460acn8-2.5 + + v out v in gnd u2 lt1236acn8-5 jp3 jmpr 1 2 3 3 2.5v jp1 jmpr jp4 jmpr jp2 jmpr nc gnd nc nc remove to disconnect v cc and 5v ref c2 22 f 25v c1 10 f 35v c4 100 f 16v c3 10 f 35v r2 3 u3c 74hc14 u3d 74hc14 u3b 74hc14 u3a 74hc14 u3e 74hc14 u3f 74hc14 r1 10 e1 e2 bypass capacitor for u3 and u4 v ext 2414/18 f51 9 d1 bav74lt1 10 applicatio s i for atio wu uu
ltc2414/LTC2418 46 241418f figure 52. LTC2418 demo program display figure 53. pcb layout and film top silkscreen top layer bottom layer applicatio s i for atio wu uu
ltc2414/LTC2418 47 241418f u package descriptio gn package 28-lead plastic ssop (narrow .150 inch) (reference ltc dwg # 05-08-1641) 0.386 ?0.393* (9.804 ?9.982) gn28 (ssop) 1098 * dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side ** dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side 12 3 4 5 6 7 8 9 10 11 12 0.229 ?0.244 (5.817 ?6.198) 0.150 ?0.157** (3.810 ?3.988) 20 21 22 23 24 25 26 27 28 19 18 17 13 14 16 15 0.016 ?0.050 (0.406 ?1.270) 0.015 0.004 (0.38 0.10) 45 0 ?8 typ 0.0075 ?0.0098 (0.191 ?0.249) 0.053 ?0.069 (1.351 ?1.748) 0.008 ?0.012 (0.203 ?0.305) 0.004 ?0.009 (0.102 ?0.249) 0.0250 (0.635) bsc 0.033 (0.838) ref information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
ltc2414/LTC2418 48 241418f linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 l fax: (408) 434-0507 l www.linear.com ? linear technology corporation 2002 lt/tp 1002 2k ? printed in usa part number description comments lt1019 precision bandgap reference, 2.5v, 5v 3ppm/ c drift, 0.05% max initial accuracy lt1025 micropower thermocouple cold junction compensator 80 m a supply current, 0.5 c initial accuracy ltc1050 precision chopper stabilized op amp no external components 5 m v offset, 1.6 m v p-p noise lt1236a-5 precision bandgap reference, 5v 0.05% max initial accuracy, 5ppm/ c drift lt1460 micropower series reference 0.075% max initial accuracy, 10ppm/ c max drift ltc2400 24-bit, no latency ds adc in so-8 0.3ppm noise, 4ppm inl, 10ppm total unadjusted error, 200 m a ltc2401/ltc2402 1-/2-channel, 24-bit, no latency ds adc in msop 0.6ppm noise, 4ppm inl, 10ppm total unadjusted error, 200 m a ltc2404/ltc2408 4-/8-channel, 24-bit, no latency ds adc 0.3ppm noise, 4ppm inl, 10ppm total unadjusted error, 200 m a ltc2410 24-bit, fully differential, no latency ds adc 0.16ppm noise, 2ppm inl, 3ppm total unadjusted error, 200 m a ltc2411 24-bit, fully differential, no latency ds adc in msop 0.3ppm noise, 2ppm inl, 3ppm total unadjusted error, 200 m a ltc2411-1 24-bit, simultaneous 50hz/60hz rejection ds adc 0.3ppm noise, 2ppm inl, pin compatible with ltc2411 ltc2413 24-bit, fully differential, no latency ds adc simultaneous 50hz and 60hz rejection, 800nv rms noise ltc2415/ltc2415-1 24-bit, no latency ds adc with 15hz output rate pin compatible with the ltc2410/ltc2413 ltc2420 20-bit, no latency ds adc in so-8 1.2ppm noise, 8ppm inl, pin compatible with ltc2400 ltc2424/ltc2428 4-/8-channel, 20-bit, no latency ds adc 1.2ppm noise, pin compatible with ltc2404/ltc2408 related parts u typical applicatio figure 54. multichannel bridge digitizer and digital cold junction compensation 11 12 21 22 23 24 7 8 10 gnd v cc LTC2418 5v 9 15 0.1 f 2418 f54 10 f sdi sck sdo cs f o ref + ref ch0 ch1 ch2 ch3 ch14 ch15 com thermistor thermocouple LTC2418 gnd v cc 20 18 17 16 19 +

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